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This avoids confusion with the released tarballs.
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No interpretation of register bits, nor attempting to decode packet contents,
but all shifted register addresses and long register memory regions are
decoded.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Decodes reads/writes of registers. Understands resetting on chip select if
provided. Does not understand burst mode.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Include their compatibility in the dropdown options too.
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This is in preparation of making the PD more generic so it can support
a lot more xx25 series SPI (NOR) flash chips.
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For Windows builds (which require MinGW-w64) we currently support:
- cross-builds using MXE (mxe.cc) and possibly other cross-compile setups
- native builds using MSYS2 (sf.net/projects/msys2/)
Neither of those require explicitly specifying ACLOCAL_DIR.
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The code was trying to emit annotations before
self.register(srd.OUTPUT_ANN) was run.
This fixes bug #357.
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Avoid decoding and outputting data from the SPI bus if the CS pin
hasn't been asserted. This avoids confusing both users and stacked
decoders which otherwise end up seeing traffic intended for other
chips (or just noise).
Note: The old behavior of decoding all traffic is still in place if
no CS pin has been wired up to the decoder.
This fixes bug #559.
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Fixed:
- wrong address decoding for some branches
- error in annotation lists for exception entry/exit
- exception was being thrown for 0E0N p-header packets
- fixes to objdump output parsing, better function name & source code matching
New features:
- added decoding of IRQ names for branch exception info
- added support for -C option to objdump to decode C++ symbol names
- put branches on the "Exceptions" annotation row when they contain exception info.
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Use g_malloc*() for small allocations and assume they always
succeed. Simplify error handling in a few places accordingly.
Document the rules in the README file.
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This allows for easily extending the PD to support other clones or
compatibles of the nRF24L01(+) chip as well.
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At 3 samples per bit, the uart decoder took the value at the last sample
instead of the middle one. Improve calculations so that sampling is more
accurate at odd number of samples per bit.
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This one can take a while, thus disable the timeout.
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This fixes bug #424.
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This also outputs one item of OUT_BINARY per jitter value (not one
item per ASCII character in the ASCII floating point number).
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Reworked in the algorithm:
- Fixed the polarity setting
- Taken in consideration the first transition
- Using the 'None' state instead of -1 and 0 value
- Simplify the algorithm and remove useless branches and variables
- Avoid re-calculating the same thing more than once
- Renamed a few variables for a better understanding
- Duty cycle precision changed to floating value
Otherwise:
- Added a meta OUTPUT for the duty cycle average
- Renamed the polarity option:
'polarity', 'active low/high' are well-understood terms.
- Added comments
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Wait for the CS# line to be inactive before decoding the commands.
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This could previously be detected by the absence of a CS-CHANGE packet
before the first data packet, but it makes the stacked decoder simpler
if it is told directly.
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