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| author | Petteri Aimonen <jpa@git.mail.kapsi.fi> | 2015-02-15 19:08:36 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-02-17 19:28:10 +0100 |
| commit | b5712ccbbcd023e5ac20d790bf75af3c18fc66d5 (patch) | |
| tree | 192d7448312a45c82f6a8a8cad36daa5a9099126 | |
| parent | 2590c098bb44f660a9668db66deaf59f3a7a651b (diff) | |
| download | libsigrokdecode-b5712ccbbcd023e5ac20d790bf75af3c18fc66d5.tar.gz libsigrokdecode-b5712ccbbcd023e5ac20d790bf75af3c18fc66d5.zip | |
Improve uart decoder sample positions at high data rates.
At 3 samples per bit, the uart decoder took the value at the last sample
instead of the middle one. Improve calculations so that sampling is more
accurate at odd number of samples per bit.
| -rw-r--r-- | decoders/uart/pd.py | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index d59c6c3..7995e99 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -19,6 +19,7 @@ ## import sigrokdecode as srd +from math import floor, ceil ''' OUTPUT_PYTHON format: @@ -139,24 +140,24 @@ class Decoder(srd.Decoder): ) def putx(self, rxtx, data): - s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) - self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data) def putpx(self, rxtx, data): - s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) - self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data) + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data) def putg(self, data): - s, halfbit = self.samplenum, int(self.bit_width / 2) - self.put(s - halfbit, s + halfbit, self.out_ann, data) + s, halfbit = self.samplenum, self.bit_width / 2.0 + self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data) def putp(self, data): - s, halfbit = self.samplenum, int(self.bit_width / 2) - self.put(s - halfbit, s + halfbit, self.out_python, data) + s, halfbit = self.samplenum, self.bit_width / 2.0 + self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) def putbin(self, rxtx, data): - s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) - self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data) + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_bin, data) def __init__(self, **kwargs): self.samplerate = None @@ -189,7 +190,9 @@ class Decoder(srd.Decoder): # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). - bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) + # The samples within bit are 0, 1, ..., (bit_width - 1), therefore + # index of the middle sample within bit window is (bit_width - 1) / 2. + bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0 bitpos += bitnum * self.bit_width if self.samplenum >= bitpos: return True |