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-rw-r--r--i2s/2ch-16bit-16khz/README3
1 files changed, 2 insertions, 1 deletions
diff --git a/i2s/2ch-16bit-16khz/README b/i2s/2ch-16bit-16khz/README
index 2c24397..5403a16 100644
--- a/i2s/2ch-16bit-16khz/README
+++ b/i2s/2ch-16bit-16khz/README
@@ -8,7 +8,7 @@ shipping forecast through one channel, and the other channel disconnected.
Logic analyzer setup
--------------------
-The logic analyzer used for capturing was a EE Electronics ESLA201A at a
+The logic analyzer used for capturing was a EE Electronics ESLA201A at a
sample rate of 16MHz. The logic analyzer probes were connected to the I2S
pins like this:
@@ -17,3 +17,4 @@ pins like this:
0 Clock
1 Frame Select
2 Data
+