diff options
| author | Matt Ranostay <mranostay@gmail.com> | 2013-03-05 20:53:53 -0800 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2013-03-06 14:08:28 +0100 |
| commit | 1b4691d8eb4e8ef82c995d205c5025647782c89d (patch) | |
| tree | fd37bd97f2681c6c0e93720097fd93fc1671b1ee /vfd | |
| parent | f3698236a25ecbaefcab1012738a86dbd74e224f (diff) | |
| download | sigrok-dumps-1b4691d8eb4e8ef82c995d205c5025647782c89d.tar.gz sigrok-dumps-1b4691d8eb4e8ef82c995d205c5025647782c89d.zip | |
Added MAX6921 shift register signal dumps.
MAX6921 signal dump that is from a prototype nixie clock
design for the AM335x-based Beaglebone.
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
Diffstat (limited to 'vfd')
| -rw-r--r-- | vfd/max6921/README | 65 | ||||
| -rw-r--r-- | vfd/max6921/max6921_data_10mhz.sr | bin | 0 -> 1199 bytes |
2 files changed, 65 insertions, 0 deletions
diff --git a/vfd/max6921/README b/vfd/max6921/README new file mode 100644 index 0000000..a71a3fa --- /dev/null +++ b/vfd/max6921/README @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------- +MAX6921 Shift Register +------------------------------------------------------------------------------- + +This is a capture of data output to a MAX6921 high voltage shift register that +was outputting data for a VFD clock. + +The signals were grabbed on a 28-pin PLCC chip (MAX6921) which outputs 20-bits +that is crafted as a design for VFD applications. + +Logic analyzer setup +-------------------- + +The logic analyzer used was Open Bench Logic Sniffer (at 10Mhz): + + Probe MAX6921 Pin + -------------------------- + 0 LOAD + 1 DATA + 2 CLK + 3 BLANK (PWM Brightness Control) + +Data +---- + +The data contain various values for the VFD being driven, as reference at the +prototype Nixie Cape for the Beaglebone. + + Digit Bit + -------------------------- + 0 1<<12 + 1 1<<19 + 2 1<<13 + 3 1<<18 + 4 1<<14 + 5 1<<17 + 6 1<<16 + 7 1<<15 + 8 1<<15 + 9 1<<11 + + Segment Bit + --------------------------- + SEG_A 1<<0 + SEG_B 1<<1 + SEG_C 1<<2 + SEG_D 1<<3 + SEG_E 1<<4 + SEG_F 1<<5 + SEG_G 1<<6 + SEG_H 1<<7 + + +References: +----------- + + * BeagleBoard.org Vendor Tree (https://github.com/beagleboard/kernel) + * Beagle Nixie GitHub (https://github.com/mranostay/beagle-nixie/) + * MAX6921 Datasheet (http://datasheets.maximintegrated.com/en/ds/MAX6921-MAX6931.pdf) + +The sigrok command line used was: + + sigrok-cli --driver=ols:conn=/dev/ttyACM0 -d samplerate=10mhz \ + -samples=24576 -p 0=LOAD,1=DATA,2=CLK,3=BLANK -o max6921_data_10mhz.sr + diff --git a/vfd/max6921/max6921_data_10mhz.sr b/vfd/max6921/max6921_data_10mhz.sr Binary files differnew file mode 100644 index 0000000..25b4500 --- /dev/null +++ b/vfd/max6921/max6921_data_10mhz.sr |