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| author | Bart de Waal <bart@waalamo.com> | 2015-03-04 00:19:53 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-03-10 21:41:11 +0100 |
| commit | bfe7c79900a7321f332e333a592bbbd596090f3c (patch) | |
| tree | 717b9bf71c8fa9cc2546fd9c146fc41dd5b15a37 /uart/modbus_rtu/brainchild_io_16do/README | |
| parent | 980c65ccac9f78131a004e7f2dafc5756bdde951 (diff) | |
| download | sigrok-dumps-bfe7c79900a7321f332e333a592bbbd596090f3c.tar.gz sigrok-dumps-bfe7c79900a7321f332e333a592bbbd596090f3c.zip | |
Add a dump from a Modbus IO module
Diffstat (limited to 'uart/modbus_rtu/brainchild_io_16do/README')
| -rw-r--r-- | uart/modbus_rtu/brainchild_io_16do/README | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/uart/modbus_rtu/brainchild_io_16do/README b/uart/modbus_rtu/brainchild_io_16do/README new file mode 100644 index 0000000..7238b97 --- /dev/null +++ b/uart/modbus_rtu/brainchild_io_16do/README @@ -0,0 +1,37 @@ +------------------------------------------------------------------------------- +Brainchild IO-16DO Modbus communication +------------------------------------------------------------------------------- + +This is a dump of Modbus data from a Brainchild IO-16DO module. + +It was connected to a PC using a Prolific USB-RS232 converter and a cheap +Chinese RS232-RS485 converter. + +Details: +http://www.brainchild.com.tw/en/2_1752_41579/product/16_digital_outputs_id147280.html + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Saleae Logic16 clone (at 1MHz). + +It was connected on the RS232 line. +The probes were connected through 10K resistors. + + Probe UART + ---------------- + 0 RX + 1 TX + + +Data +---- + +The sigrok command line used was: + + sigrok-cli -C 0,1 -c "samplerate=1 MHz" -d saleae-logic16 -o \ + brainchild-io-16do.sr --time 300ms + +The requests were sent with the included brainchild-io-16do-activity.py script. + |