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authorGerhard Sittig <gerhard.sittig@gmx.net>2020-08-18 20:19:42 +0200
committerGerhard Sittig <gerhard.sittig@gmx.net>2020-08-18 20:26:11 +0200
commitf114ba0bba39d6e0dd266a492d3c8ddda5cd5a38 (patch)
tree313fde951148d68f7cb9a69c713f19fd2bde97da /sle44xx/README
parent7afb7efea42212892a6bd052542e87debcbeb9e3 (diff)
downloadsigrok-dumps-f114ba0bba39d6e0dd266a492d3c8ddda5cd5a38.tar.gz
sigrok-dumps-f114ba0bba39d6e0dd266a492d3c8ddda5cd5a38.zip
sle44xx: extend the README for the SLE4442 captures
Create a README in the sle44xx/ parent directory, discuss the chip family's features, and reference the Siemens datasheet. Extend the README for the SLE4442 captures, don't assume that all users are familiar with the chips and their protocol. The example dumps also serve for learning and exploration of the curious. Fixup the probe names (according to --show their names are in the 0..7 range).
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+------------------------------------------------------------------------
+Siemens SLE44xx Chip Card Protocol
+------------------------------------------------------------------------
+
+SLE 4418/4428/4432/4442 memory cards implement a 2-wire protocol for data
+communication (signals CLK and I/O). A RST signal can be used to terminate
+currently pending long memory reads, and resets the card's address counter
+when combined with CLK. The next response data then is the Answer to Reset
+(ATR) which identifies the chip's capabilities, and allows to adjust for
+subsequent communication of more requests.
+
+See the Siemens document for details:
+
+ ICs for Chip Cards
+ Intelligent 256-Byte EEPROM
+ SLE 4432/SLE 4442
+ Data Sheet 07.95
+
+
+Logic analyzer setup
+--------------------
+
+ Probe SLE44xx
+ ----------------
+ 0 I/O
+ 1 CLK
+ 2 RST
+
+See subdirectories for chip specific example files.