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author | Uwe Hermann <uwe@hermann-uwe.de> | 2019-04-30 19:17:10 +0200 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2019-04-30 22:23:14 +0200 |
commit | c7692e182af6f603db6511ebae5109723cab42f1 (patch) | |
tree | e320b90759e0a279a4862ed20ee3b73f48fa7db1 /i2s/2ch-32bit-8khz/README | |
parent | d8a0e7a8001659ad69f9b556e97563560738c967 (diff) | |
download | sigrok-dumps-c7692e182af6f603db6511ebae5109723cab42f1.tar.gz sigrok-dumps-c7692e182af6f603db6511ebae5109723cab42f1.zip |
Rename 2ch-16bit-16khz to 2ch-32bit-8khz.
https://github.com/sigrokproject/libsigrokdecode/pull/6#issuecomment-442025810
Diffstat (limited to 'i2s/2ch-32bit-8khz/README')
-rw-r--r-- | i2s/2ch-32bit-8khz/README | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/i2s/2ch-32bit-8khz/README b/i2s/2ch-32bit-8khz/README new file mode 100644 index 0000000..c629dc4 --- /dev/null +++ b/i2s/2ch-32bit-8khz/README @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------- +I2S Master 2-channel 32-bit 8-kHz +------------------------------------------------------------------------------- + +This is an example of an I2S master playing a recording of the BBC +shipping forecast through one channel, and the other channel disconnected. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was an EE Electronics ESLA201A (at 12MHz): + + Probe I2S pin + ------------------- + 0 Clock + 1 Frame Select + 2 Data |