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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2012-12-28 22:59:12 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2012-12-28 22:59:12 +0100 |
| commit | e467132dcbfa83a0ec0a4fd64ddd00c64f91f04e (patch) | |
| tree | 900ed8e8b321c305fa2f4bd916b0be0384c987bb | |
| parent | abdaf3290a42626ecfb7ea870d34c1e5defa6527 (diff) | |
| download | sigrok-dumps-e467132dcbfa83a0ec0a4fd64ddd00c64f91f04e.tar.gz sigrok-dumps-e467132dcbfa83a0ec0a4fd64ddd00c64f91f04e.zip | |
Add sample 1MHz clock signal dumps.
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_16channels.sr | bin | 0 -> 77482 bytes | |||
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_1channels.sr | bin | 0 -> 42419 bytes | |||
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_4channels.sr | bin | 0 -> 42572 bytes | |||
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_7channels.sr | bin | 0 -> 42513 bytes | |||
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_8channels.sr | bin | 0 -> 42845 bytes | |||
| -rw-r--r-- | random/1mhz_clock/1mhz_clock_9channels.sr | bin | 0 -> 77582 bytes | |||
| -rw-r--r-- | random/1mhz_clock/README | 35 |
7 files changed, 35 insertions, 0 deletions
diff --git a/random/1mhz_clock/1mhz_clock_16channels.sr b/random/1mhz_clock/1mhz_clock_16channels.sr Binary files differnew file mode 100644 index 0000000..c9b5965 --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_16channels.sr diff --git a/random/1mhz_clock/1mhz_clock_1channels.sr b/random/1mhz_clock/1mhz_clock_1channels.sr Binary files differnew file mode 100644 index 0000000..0fdd10e --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_1channels.sr diff --git a/random/1mhz_clock/1mhz_clock_4channels.sr b/random/1mhz_clock/1mhz_clock_4channels.sr Binary files differnew file mode 100644 index 0000000..6cc3e06 --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_4channels.sr diff --git a/random/1mhz_clock/1mhz_clock_7channels.sr b/random/1mhz_clock/1mhz_clock_7channels.sr Binary files differnew file mode 100644 index 0000000..0c84367 --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_7channels.sr diff --git a/random/1mhz_clock/1mhz_clock_8channels.sr b/random/1mhz_clock/1mhz_clock_8channels.sr Binary files differnew file mode 100644 index 0000000..30f52fc --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_8channels.sr diff --git a/random/1mhz_clock/1mhz_clock_9channels.sr b/random/1mhz_clock/1mhz_clock_9channels.sr Binary files differnew file mode 100644 index 0000000..fc7504a --- /dev/null +++ b/random/1mhz_clock/1mhz_clock_9channels.sr diff --git a/random/1mhz_clock/README b/random/1mhz_clock/README new file mode 100644 index 0000000..a715bca --- /dev/null +++ b/random/1mhz_clock/README @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +1MHz clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a digital 1MHz clock signal (rectangle +signal) generated using a function generator, sampled using a logic analyzer. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): + + Probe Signal + ----------------------------- + 1 1MHz clock signal + + +Data +---- + +The sigrok command line used was: + + sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ + -o <filename> -p XXXX + +XXXX specifies how many probes to sample/save: + + - 1 signal: -p 1 + - 4 signals: -p 1-4 + - 7 signals: -p 1-7 + - 8 signals: -p 1-8 + - 9 signals: -p 1-9 + - 16 signals: -p 1-16 + |