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Add support for register field content checkers, and emit warning
annotations when they yield non-empty results. Implement a checker for
the INT field of register R0. Reduce the allowed values' lower limit
from 32 (previous implementation) to 23 (ADF4350 datasheet, figure 24).
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Move table columns, put the bit field position to the front before the
name to get a less fragile visual appearance. All fields have a position
and a name (of variable length), some of them have a "parser" (actually
a formatter for their content).
Address Python style while we are here: Prefer tuples over lists for
immutable data. Add trailing commas to reduce future diff sizes.
Add a TODO comment about optional content checkers. The current decoder
implementation lets invalid register data pass unnoticed.
[ see a word diff for the commit's essence ]
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Try a different presentation of exising information in the register
fields' display text construction (extra parsers for known fields).
Attempt a source code format which hopefully better lends itself to
index range verification during review.
Make the number of available expansion texts stand out more visually,
so that readers can compare their count to the register field's width.
Address those register fields with four or more expansion values, keep
the simple single bit cases as they are. Add a comment for awareness.
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Rephrase the old style '%' operator string formatting, prefer .format()
calls instead. It is assumed that routine call argument lists are more
readable than optional/conditional tuples are, and not running format
specifiers and literal text into each other helps readability as well,
as do the .format() routine's optionally named references to parameters.
Avoid text formatting which involves concatenation, always work from one
single format instruction instead.
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Move the inspection of a completed 32bit word into the .decode_word()
routine. This simplifies checks for fatal constraints, as well as
optional inspection of deeper detail levels when extra parsers are
available.
Rename variables in the code path which accumulate bits. Add comments
to helper routines and to essential steps in complex interpretation
code paths. Eliminate the unused return value of the .decode_field()
method. Results in a lean and readable .decode() body.
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Separate data processing from text formatting in the code paths which
emit annotations. Introduce a local .putg() helper. This unobfuscates
the decoder's operation, and also happens to shorten text lines. Raises
awareness for zoom levels and alternative text during maintenance.
This commit incompatibly rephrases the "Wrong number of bits" message.
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Use .extend() and .clear() for the Python list during accumulation of a
32bit word's bits sequence. This shall improve readability. Performance
is less of an issue since this decoder's data amount remains small
(32bit entities per SPI transfer).
Comment on the unexpected(?) SPI decoder's BITS ordering when passing
details up to stacked decoders. Raise and keep awareness for this
non-obvious implementation detail during decoder maintenance.
This implementation accumulates bits in the MSB order as they are sent
in SPI frames. Yet keeps the LSB bit order when a completely accumulated
32bit word gets inspected, to reduce the diff size. Bit field extraction
and annotation emission code paths assume a specific timestamp ordering.
The separation of transport and inspection also simplifies maintenance,
should a future SPI decoder provide BITS in their received order.
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Use common support code to convert bit fields to integer numbers. Also
unobfuscate the decode_bits() method and its returned values' layout.
Improves readability and factors out common expressions.
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The previous implementation of the ADF435x decoder assumed knowledge of
internal details which are the SPI transport layer's responsibility. And
encoded an inappropriate chip select polarity in the process (falling
CS edge). The datasheet specifies that previously clocked in data bits
get latched on rising LE edges.
Not all setups were affected, that's why the issue went unnoticed before.
Use the lower layer's TRANSFER annotation to process the completion of
an ADF435x register access, after BITS annotations made the location of
individual bits available. The LE (CS) signal's polarity remains a detail
of the SPI decoding layer, and must be configured there. The SPI decoder's
default matches the ADF435x chip's expectation.
This fixes bug #1814.
Reported-by: Martin Homuth-Rosemann <homuth-rosemann@gmx.net>
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Check the bit count of SPI transfers. Only start inspecting ADF435x
register content when the accumulation of the expected 32bit word has
completed. Emit a warning annotation for unexpected transfer sizes.
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Avoid generic variable names. Only unpack parameters which are provided
by the lower layer decoder after the stacked decoder checked their type
and is aware of their meaning.
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Only add items to 'outputs' if the respective PD actually has
OUTPUT_PYTHON support implemented as of right now.
Various decoders might get OUTPUT_PYTHON support later, but the
'outputs' field should reflect the current status.
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Move initialization code of protocol decoders from the constructor to a
new reset() helper method. The libsigrokdecode backend could run this
method several times to clear the decoder's internal state, before new
data from another acquisition gets fed to decode() calls.
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This is not really relevant for stacked PDs currently (they can be used
unmodified with either PDv2 or PDv3 low-level decoders), but it'll allow
us to drop PDv2 support completely.
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