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| author | Bert Vermeulen <bert@biot.com> | 2012-01-21 15:04:47 +0100 |
|---|---|---|
| committer | Bert Vermeulen <bert@biot.com> | 2012-01-21 15:06:21 +0100 |
| commit | 4244f8252706c5715a5598c51914f4f8d20c5e84 (patch) | |
| tree | fec52f175ac85b530fc1fc607760257319fa641e /type_logic.c | |
| parent | f38ec2855ce41154bc1035dd7f1ab9a21f411f0d (diff) | |
| download | libsigrokdecode-4244f8252706c5715a5598c51914f4f8d20c5e84.tar.gz libsigrokdecode-4244f8252706c5715a5598c51914f4f8d20c5e84.zip | |
srd: fix probe mapping
Diffstat (limited to 'type_logic.c')
| -rw-r--r-- | type_logic.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/type_logic.c b/type_logic.c index 28c3670..7cea75b 100644 --- a/type_logic.c +++ b/type_logic.c @@ -48,10 +48,8 @@ PyObject *srd_logic_iternext(PyObject *self) */ memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize, logic->di->data_unitsize); - for (i = 0; i < logic->di->dec_num_probes; i++) { - probe_samples[logic->di->dec_probemap[i]] = sample & 0x01; - sample >>= 1; - } + for (i = 0; i < logic->di->dec_num_probes; i++) + probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; /* Prepare the next samplenum/sample list in this iteration. */ py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt); |