From 4244f8252706c5715a5598c51914f4f8d20c5e84 Mon Sep 17 00:00:00 2001 From: Bert Vermeulen Date: Sat, 21 Jan 2012 15:04:47 +0100 Subject: srd: fix probe mapping --- type_logic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'type_logic.c') diff --git a/type_logic.c b/type_logic.c index 28c3670..7cea75b 100644 --- a/type_logic.c +++ b/type_logic.c @@ -48,10 +48,8 @@ PyObject *srd_logic_iternext(PyObject *self) */ memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize, logic->di->data_unitsize); - for (i = 0; i < logic->di->dec_num_probes; i++) { - probe_samples[logic->di->dec_probemap[i]] = sample & 0x01; - sample >>= 1; - } + for (i = 0; i < logic->di->dec_num_probes; i++) + probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; /* Prepare the next samplenum/sample list in this iteration. */ py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt); -- cgit v1.2.3-70-g09d2