spiflash: Initial RDSR2 implementation (incomplete).

This is not entirely correct yet, will be fixed later.

2 files changed, 17 insertions, 0 deletions

diff --git a/decoders/spiflash/lists.py b/decoders/spiflash/lists.py
index 9a06992..a692119 100644
--- a/decoders/spiflash/lists.py
+++ b/decoders/spiflash/lists.py
@@ -24,6 +24,7 @@ cmds = {
     0x04: ('WRDI', 'Write disable'),
     0x9f: ('RDID', 'Read identification'),
     0x05: ('RDSR', 'Read status register'),
+    0x35: ('RDSR2', 'Read status register 2'),
     0x01: ('WRSR', 'Write status register'),
     0x03: ('READ', 'Read data'),
     0x0b: ('FAST/READ', 'Fast read data'),
diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index 3afafba..4c5c06b 100644
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -173,6 +173,22 @@ class Decoder(srd.Decoder):
 
         self.cmdstate += 1
 
+    def handle_rdsr2(self, mosi, miso):
+        # Read status register 2: Master asserts CS#, sends RDSR2 command,
+        # reads status register 2 byte. If CS# is kept asserted, the status
+        # register 2 can be read continuously / multiple times in a row.
+        # When done, the master de-asserts CS# again.
+        if self.cmdstate == 1:
+            # Byte 1: Master sends command ID.
+            self.putx([3, ['Command: %s' % cmds[self.state][1]]])
+        elif self.cmdstate >= 2:
+            # Bytes 2-x: Slave sends status register 2 as long as master clocks.
+            self.putx([24, ['Status register 2: 0x%02x' % miso]])
+            self.putx([25, [decode_status_reg(miso)]])
+            # TODO: Handle status register 2 correctly.
+
+        self.cmdstate += 1
+
     def handle_wrsr(self, mosi, miso):
         # Write status register: Master asserts CS#, sends WRSR command,
         # writes 1 or 2 status register byte(s).