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authorUwe Hermann <uwe@hermann-uwe.de>2016-11-06 17:49:28 +0100
committerUwe Hermann <uwe@hermann-uwe.de>2016-11-07 02:01:00 +0100
commit0a89f2ae27d7ba9e6f009df9745f45c4524234fd (patch)
tree6e588eb98229692d637c451646dc1000bb348e76 /decoders
parent03ec43f06ea5675828316228f4e26f8152859c99 (diff)
downloadlibsigrokdecode-0a89f2ae27d7ba9e6f009df9745f45c4524234fd.tar.gz
libsigrokdecode-0a89f2ae27d7ba9e6f009df9745f45c4524234fd.zip
spiflash: Implement WRSR command.
Diffstat (limited to 'decoders')
-rw-r--r--decoders/spiflash/pd.py15
1 files changed, 14 insertions, 1 deletions
diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index d33ac0c..3afafba 100644
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -174,7 +174,20 @@ class Decoder(srd.Decoder):
self.cmdstate += 1
def handle_wrsr(self, mosi, miso):
- pass # TODO
+ # Write status register: Master asserts CS#, sends WRSR command,
+ # writes 1 or 2 status register byte(s).
+ # When done, the master de-asserts CS# again. If this doesn't happen
+ # the WRSR command will not be executed.
+ if self.cmdstate == 1:
+ # Byte 1: Master sends command ID.
+ self.putx([3, ['Command: %s' % cmds[self.state][1]]])
+ elif self.cmdstate in (2, 3):
+ # Bytes 2 and/or 3: Master sends status register byte(s).
+ self.putx([24, ['Status register: 0x%02x' % miso]])
+ self.putx([25, [decode_status_reg(miso)]])
+ # TODO: Handle status register 2 correctly.
+
+ self.cmdstate += 1
def handle_read(self, mosi, miso):
# Read data bytes: Master asserts CS#, sends READ command, sends