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authorUwe Hermann <uwe@hermann-uwe.de>2016-09-24 12:22:57 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2016-09-24 12:25:10 +0200
commitc1fc50b1256dba3bfad7e769691f11b729601b28 (patch)
treef25366309af0bb9887772e3cfb9caf9559853fbd /decoders/uart/pd.py
parenteb6360c9b161e77c6a04479a08c581306ffb9818 (diff)
downloadlibsigrokdecode-c1fc50b1256dba3bfad7e769691f11b729601b28.tar.gz
libsigrokdecode-c1fc50b1256dba3bfad7e769691f11b729601b28.zip
uart: Fix a bug in the output for stacked PDs.
The UART bit information was not transmitted correctly to stacked PDs if there was an overlap between RX and TX bytes in the data.
Diffstat (limited to 'decoders/uart/pd.py')
-rw-r--r--decoders/uart/pd.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 0e6e548..151cae4 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -288,7 +288,7 @@ class Decoder(srd.Decoder):
self.putbin(rxtx, [rxtx, bytes([b])])
self.putbin(rxtx, [2, bytes([b])])
- self.databits = [[], []]
+ self.databits[rxtx] = []
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.