From c1fc50b1256dba3bfad7e769691f11b729601b28 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sat, 24 Sep 2016 12:22:57 +0200 Subject: uart: Fix a bug in the output for stacked PDs. The UART bit information was not transmitted correctly to stacked PDs if there was an overlap between RX and TX bytes in the data. --- decoders/uart/pd.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'decoders/uart/pd.py') diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 0e6e548..151cae4 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -288,7 +288,7 @@ class Decoder(srd.Decoder): self.putbin(rxtx, [rxtx, bytes([b])]) self.putbin(rxtx, [2, bytes([b])]) - self.databits = [[], []] + self.databits[rxtx] = [] def get_parity_bit(self, rxtx, signal): # If no parity is used/configured, skip to the next state immediately. -- cgit v1.2.3-70-g09d2