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| author | Vesa-Pekka Palmu <vpalmu@depili.fi> | 2018-10-18 01:57:28 +0300 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2018-10-21 17:37:04 +0200 |
| commit | bb2cda30325a7e01a77dd30aeed67b142837d822 (patch) | |
| tree | a09281c6058d8f5e711404a607942a368aeb793f /decoders/spiflash | |
| parent | 2e3e0840d6cc8ad16b9964dcf5615371591e7f9f (diff) | |
| download | libsigrokdecode-bb2cda30325a7e01a77dd30aeed67b142837d822.tar.gz libsigrokdecode-bb2cda30325a7e01a77dd30aeed67b142837d822.zip | |
spiflash: Remember write protection latch from status registers
Diffstat (limited to 'decoders/spiflash')
| -rw-r--r-- | decoders/spiflash/pd.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py index 3d525b9..aecc2d3 100644 --- a/decoders/spiflash/pd.py +++ b/decoders/spiflash/pd.py @@ -217,6 +217,8 @@ class Decoder(srd.Decoder): self.putx([Ann.BIT, [decode_status_reg(miso)]]) self.putx([Ann.FIELD, ['Status register']]) self.putc([Ann.RDSR, self.cmd_ann_list()]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 self.cmdstate += 1 def handle_rdsr2(self, mosi, miso): @@ -248,6 +250,8 @@ class Decoder(srd.Decoder): # Byte 2: Master sends status register 1. self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 1']]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 elif self.cmdstate == 3: # Byte 3: Master sends status register 2. # TODO: Decode status register 2 correctly. |