From bb2cda30325a7e01a77dd30aeed67b142837d822 Mon Sep 17 00:00:00 2001 From: Vesa-Pekka Palmu Date: Thu, 18 Oct 2018 01:57:28 +0300 Subject: spiflash: Remember write protection latch from status registers --- decoders/spiflash/pd.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'decoders/spiflash') diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py index 3d525b9..aecc2d3 100644 --- a/decoders/spiflash/pd.py +++ b/decoders/spiflash/pd.py @@ -217,6 +217,8 @@ class Decoder(srd.Decoder): self.putx([Ann.BIT, [decode_status_reg(miso)]]) self.putx([Ann.FIELD, ['Status register']]) self.putc([Ann.RDSR, self.cmd_ann_list()]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 self.cmdstate += 1 def handle_rdsr2(self, mosi, miso): @@ -248,6 +250,8 @@ class Decoder(srd.Decoder): # Byte 2: Master sends status register 1. self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 1']]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 elif self.cmdstate == 3: # Byte 3: Master sends status register 2. # TODO: Decode status register 2 correctly. -- cgit v1.2.3-70-g09d2