diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2012-01-14 18:08:00 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2012-01-14 18:08:00 +0100 |
| commit | 1ea831e97a3c65b820c049220480def1636cb0b5 (patch) | |
| tree | 8d439fffe429f5448c1dc2a589d50b88abb9bcf1 /decoders/spi.py | |
| parent | 0db89774dee57db500f270985f73f3bb2dcdbb42 (diff) | |
| download | libsigrokdecode-1ea831e97a3c65b820c049220480def1636cb0b5.tar.gz libsigrokdecode-1ea831e97a3c65b820c049220480def1636cb0b5.zip | |
srd: SPI: Add support for bit order option.
Diffstat (limited to 'decoders/spi.py')
| -rw-r--r-- | decoders/spi.py | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/decoders/spi.py b/decoders/spi.py index 457abb5..0c98c1d 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -112,11 +112,17 @@ class Decoder(srd.Decoder): if self.bitcount == 0: self.start_sample = samplenum - # Receive bit into our shift register. - if mosi == 1: - self.mosidata |= 1 << (7 - self.bitcount) - if miso == 1: - self.misodata |= 1 << (7 - self.bitcount) + # Receive MOSI bit into our shift register. + if self.bit_order == MSB_FIRST: + self.mosidata |= mosi << (7 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount + + # Receive MISO bit into our shift register. + if self.bit_order == MSB_FIRST: + self.misodata |= miso << (7 - self.bitcount) + else: + self.misodata |= miso << self.bitcount self.bitcount += 1 |