diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2017-05-05 08:45:07 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2017-05-05 19:19:26 +0200 |
| commit | fe9e9cebf035708240350b4fe80a676112130074 (patch) | |
| tree | 81dc674e60e9a2ee6ec7320556975f52998c258c | |
| parent | 13c484ddd3156c70bb1257208bdae839e463a24e (diff) | |
| download | libsigrokdecode-fe9e9cebf035708240350b4fe80a676112130074.tar.gz libsigrokdecode-fe9e9cebf035708240350b4fe80a676112130074.zip | |
microwire: Drop some trailing whitespace.
| -rw-r--r-- | decoders/microwire/pd.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/decoders/microwire/pd.py b/decoders/microwire/pd.py index e64732d..2724c78 100644 --- a/decoders/microwire/pd.py +++ b/decoders/microwire/pd.py @@ -29,7 +29,7 @@ Packet: 'so': SO bit, }, ...] -Since address and word size are variable, a list of all bits in each packet +Since address and word size are variable, a list of all bits in each packet need to be output. Since Microwire is a synchronous protocol with separate input and output lines (SI and SO) they are provided together, but because Microwire is half-duplex only the SI or SO bits will be considered at once. @@ -119,16 +119,16 @@ class Decoder(srd.Decoder): if len(change['matched']) > 2 and change['matched'][2]: if bit_so == 0 and change['so']: # Rising edge Busy -> Ready. - self.put(start_samplenum, change['samplenum'], + self.put(start_samplenum, change['samplenum'], self.out_ann, [4, ['Busy', 'B']]) start_samplenum = change['samplenum'] bit_so = change['so'] # Put last state. if bit_so == 0: - self.put(start_samplenum, packet[-1]['samplenum'], + self.put(start_samplenum, packet[-1]['samplenum'], self.out_ann, [4, ['Busy', 'B']]) else: - self.put(start_samplenum, packet[-1]['samplenum'], + self.put(start_samplenum, packet[-1]['samplenum'], self.out_ann, [3, ['Ready', 'R']]) else: # Bit communication. |