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authorUwe Hermann <uwe@hermann-uwe.de>2020-04-11 01:32:56 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2020-04-11 15:09:15 +0200
commit5b6fb5aee2237543fd9f26085d0ffa3631c6cb02 (patch)
tree087d6e0d30b6ce65bcdf8e993063333d01e8c22e
parentb5d9eaab401d6c4689b1e3e9cbe4a92fb8e861b1 (diff)
downloadlibsigrokdecode-5b6fb5aee2237543fd9f26085d0ffa3631c6cb02.tar.gz
libsigrokdecode-5b6fb5aee2237543fd9f26085d0ffa3631c6cb02.zip
ad79x0: Rename the 'ref' option to 'vref'.
-rw-r--r--decoders/ad79x0/pd.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/decoders/ad79x0/pd.py b/decoders/ad79x0/pd.py
index d966ed9..3d7ab73 100644
--- a/decoders/ad79x0/pd.py
+++ b/decoders/ad79x0/pd.py
@@ -54,7 +54,7 @@ class Decoder(srd.Decoder):
('data_validation', 'Data validation', (2,)),
)
options = (
- {'id': 'ref', 'desc': 'Reference voltage', 'default': 1.5},
+ {'id': 'vref', 'desc': 'Reference voltage (V)', 'default': 1.5},
)
def __init__(self,):
@@ -108,7 +108,7 @@ class Decoder(srd.Decoder):
self.put_validation([self.start_sample, es], 'complete')
elif nb_bits < 16:
self.put_validation([self.start_sample, es], 'incomplete')
- vin = (self.data / ((2**12) - 1)) * self.options['ref']
+ vin = (self.data / ((2**12) - 1)) * self.options['vref']
self.put_data([self.start_sample, es], vin)
elif nb_bits < 10:
self.put_mode([self.start_sample, es], 1)