1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2020 Analog Devices Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 3 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
import sigrokdecode as srd
modes = {
0: ['Normal Mode', 'Normal', 'Norm', 'N'],
1: ['Power Down Mode', 'Power Down', 'PD'],
2: ['Power Up Mode', 'Power Up', 'PU'],
}
input_voltage_format = ['%.6fV', '%.2fV']
validation = {
'invalid': ['Invalid data', 'Invalid', 'N/A'],
'incomplete': ['Incomplete conversion', 'Incomplete', 'I'],
'complete': ['Complete conversion', 'Complete', 'C'],
}
class Decoder(srd.Decoder):
api_version = 3
id = 'ad79x0'
name = 'AD79x0'
longname = 'Analog Devices AD79x0'
desc = 'Analog Devices AD7910/AD7920 12-bit ADC.'
license = 'gplv2+'
inputs = ['spi']
outputs = []
tags = ['IC', 'Analog/digital']
annotations = (
('mode', 'Mode'),
('voltage', 'Voltage'),
('validation', 'Validation'),
)
annotation_rows = (
('modes', 'Modes', (0,)),
('voltages', 'Voltages', (1,)),
('data_validation', 'Data validation', (2,)),
)
options = (
{'id': 'ref', 'desc': 'Reference voltage', 'default': 1.5},
)
def __init__(self,):
self.reset()
def reset(self):
self.samplerate = 0
self.samples_bit = -1
self.ss = -1
self.start_sample = 0
self.previous_state = 0
self.data = 0
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.samplerate = value
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
def put_validation(self, pos, msg):
self.put(pos[0], pos[1], self.out_ann, [2, validation[msg]])
def put_data(self, pos, input_voltage):
ann = []
for format in input_voltage_format:
ann.append(format % input_voltage)
self.put(pos[0], pos[1], self.out_ann, [1, ann])
def put_mode(self, pos, msg):
self.put(pos[0], pos[1], self.out_ann, [0, modes[msg]])
def decode(self, ss, es, data):
ptype = data[0]
if ptype == 'CS-CHANGE':
cs_old, cs_new = data[1:]
if cs_old is not None and cs_old == 0 and cs_new == 1:
if self.samples_bit == -1:
return
self.data >>= 1
nb_bits = (ss - self.ss) // self.samples_bit
if nb_bits >= 10:
if self.data == 0xFFF:
self.put_mode([self.start_sample, es], 2)
self.previous_state = 0
self.put_validation([self.start_sample, es], 'invalid')
else:
self.put_mode([self.start_sample, es], 0)
if nb_bits == 16:
self.put_validation([self.start_sample, es], 'complete')
elif nb_bits < 16:
self.put_validation([self.start_sample, es], 'incomplete')
vin = (self.data / ((2**12) - 1)) * self.options['ref']
self.put_data([self.start_sample, es], vin)
elif nb_bits < 10:
self.put_mode([self.start_sample, es], 1)
self.previous_state = 1
self.put_validation([self.start_sample, es], 'invalid')
self.ss = -1
self.samples_bit = -1
self.data = 0
elif cs_old is not None and cs_old == 1 and cs_new == 0:
self.start_sample = ss
self.samples_bit = -1
elif ptype == 'BITS':
if data[2] is None:
return
miso = data[2]
if self.samples_bit == -1:
self.samples_bit = miso[0][2] - miso[0][1]
if self.ss == -1:
self.ss = ss
for bit in reversed(miso):
self.data = self.data | bit[0]
self.data <<= 1
|
