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path: root/decoder/test/parallel/test.conf
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test incremental_8ch_short_noclock
	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
	input misc/demo/incremental_8ch_short.sr
	output parallel annotation match incremental_8ch_short_noclock.output
	output parallel python match incremental_8ch_short_noclock.python

test incremental_8ch_short_clock
	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
	input misc/demo/incremental_8ch_short.sr
	output parallel annotation match incremental_8ch_short_clock.output
	output parallel python match incremental_8ch_short_clock.python

test incremental_8ch_long_noclock
	protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2
	input misc/demo/incremental_8ch_long.sr
	output parallel annotation match incremental_8ch_long_noclock.output
	output parallel python match incremental_8ch_long_noclock.python

test incremental_8ch_long_clock
	protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
	input misc/demo/incremental_8ch_long.sr
	output parallel annotation match incremental_8ch_long_clock.output
	output parallel python match incremental_8ch_long_clock.python

test hd44780_word_demux
	protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big
	input display/hd44780/hd44780-reset-init-hello.sr
	output parallel annotation match hd44780_word_demux.output

test spi_sqi_four_lines_one_xfer
	protocol-decoder parallel channel clk=2 channel d0=4 channel d1=5 channel d2=6 channel d3=7 channel rst=3 option clock_edge=rising option reset_polarity=high-active option wordsize=2 option endianness=big
	input spi/sqi/sqi-four-data-lines-one-transfer.sr
	output parallel annotation match spi_sqi_four_lines_three_transfers.output
	output parallel python match spi_sqi_four_lines_one_xfer.python