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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2018-10-21 18:12:41 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2018-10-21 18:12:41 +0200 |
| commit | 3c35aaa05492cfa60c9482634987b50c5b7b2d38 (patch) | |
| tree | 766517ed9244f78af1d5e9a4c3d699d4c93fba48 /decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output | |
| parent | 27130f5d421faf4f88ba60efe31100096bfa5b93 (diff) | |
| download | sigrok-test-3c35aaa05492cfa60c9482634987b50c5b7b2d38.tar.gz sigrok-test-3c35aaa05492cfa60c9482634987b50c5b7b2d38.zip | |
spiflash: Updates due to recent PD chages.
Diffstat (limited to 'decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output')
| -rw-r--r-- | decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output index 50f9f85..4186414 100644 --- a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output +++ b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output @@ -7,3 +7,4 @@ Status register writes are allowed. " 28-45 spiflash: field: "Status register" 8-45 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" +66-84 spiflash: ce: "Command: Chip erase (CE)" "Command: Chip erase" "Cmd: Chip erase" "Cmd: CE" "CE" |