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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2018-10-21 17:58:35 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2018-10-21 18:01:45 +0200 |
| commit | 27130f5d421faf4f88ba60efe31100096bfa5b93 (patch) | |
| tree | 5035a4f3dc587e4a14dff8af8c2df255346f8407 /decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output | |
| parent | bc622c0b72dee008a6c0098779139e21693aae4b (diff) | |
| download | sigrok-test-27130f5d421faf4f88ba60efe31100096bfa5b93.tar.gz sigrok-test-27130f5d421faf4f88ba60efe31100096bfa5b93.zip | |
spiflash: Add a few Winbond W25Q80DV tests.
Diffstat (limited to 'decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output')
| -rw-r--r-- | decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output new file mode 100644 index 0000000..50f9f85 --- /dev/null +++ b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output @@ -0,0 +1,9 @@ +8-25 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" +28-45 spiflash: bit: "No write operation in progress. +Internal write enable latch is set. +Block protection bits (BP3-BP0): 0x0. +Device is not in continuously program mode (CP mode). +Status register writes are allowed. +" +28-45 spiflash: field: "Status register" +8-45 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" |