From 27130f5d421faf4f88ba60efe31100096bfa5b93 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Oct 2018 17:58:35 +0200 Subject: spiflash: Add a few Winbond W25Q80DV tests. --- decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output (limited to 'decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output') diff --git a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output new file mode 100644 index 0000000..50f9f85 --- /dev/null +++ b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output @@ -0,0 +1,9 @@ +8-25 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" +28-45 spiflash: bit: "No write operation in progress. +Internal write enable latch is set. +Block protection bits (BP3-BP0): 0x0. +Device is not in continuously program mode (CP mode). +Status register writes are allowed. +" +28-45 spiflash: field: "Status register" +8-45 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" -- cgit v1.2.3-54-g00ecf