blob: 3dcdeb5e2fb3996f28ca90cfb54b0fd0b395503d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
-------------------------------------------------------------------------------
Arbitrary LPC (low pin count) traffic
-------------------------------------------------------------------------------
These captures are the identification and programming with random data of an
LPC (low pin count) interface flash chip. The LPC bus is emulated with an ARM
Cortex-M microcontroller, and does not run at the standard 33MHz clock.
Although the clock contains significant jitter, the connected chips respond
and communicate as expected.
Details:
http://en.wikipedia.org/wiki/Low_Pin_Count
http://www.intel.com/design/chipsets/industry/25128901.pdf
Hardware setup
--------------
A VultureProg daughterboard was attached to a TI Stellaris Launchpad board.
An SST49LF080A flash chip was installed in the PLCC socket. The core clock of
the CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to
capture all details of the waveform. The logic analyzer used was connected to
the "LPC probe" header of the VultureProg daughterboard.
Hardware: http://github.com/mrnuke/vultureprog-hardware
Firmware + SW: http://git.qiprog.org/
The logic analyzer used was an MCU123 USBee AX Pro clone (at 24MHz):
Probe LPC
----------
0 LAD0
1 LAD1
2 LAD2
3 LAD3
4 LCLK
5 LFRAME#
Data
----
lpc_vultureprog.sr:
VultureProg BIOS chip programmer programming random data to an SST49LF080A.
The bus clock was intentionally reduced to allow capture with an FX2-based
logic analyzer.
The sigrok command line used was:
sigrok-cli --driver fx2lafw --config samplerate=24mhz --samples 23552000 \
-o <filename>
This data is released into the public domain.
|
