summaryrefslogtreecommitdiff
path: root/i2c/eeprom_24xx/microchip_24lc64/README
blob: 70011f0a3ba613c5fe921a8811097e41556e8643 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
-------------------------------------------------------------------------------
Microchip 24LC64
-------------------------------------------------------------------------------

This is a set of example captures of Microchip 24LC64 I2C traffic.

Details:
https://www.microchip.com/wwwproducts/en/24LC64
http://ww1.microchip.com/downloads/en/DeviceDoc/21189T.pdf


Logic analyzer setup
--------------------

The logic analyzer used was a CWAV USBee SX or equivalent (at 8MHz):

  Probe       I2C pin
  -------------------
  0 (black)   SCL
  1 (brown)   SDA


amfpga-cpld-board-fx2-init.sr
-----------------------------

This is the I2C communication of a Microchip 24LC64 in an AMFPGA CPLD board.


instrustar_isds250a_powerup.sr
------------------------------

This is the I2C communication during powerup between the Cypress FX2 and the
Microchip 24LC64 in the Instrustar ISDS205A USB oscilloscope.


instrustar_isds205x_powerup_scope.sr
------------------------------------

This is the I2C communication during powerup between the Cypress FX2 and the
Microchip 24LC64 in the Instrustar ISDS205X USB oscilloscope (scope mode).


sainsmart_dds120_powerup.sr
---------------------------

This is the I2C communication during powerup between the Cypress FX2 and the
Microchip 24LC64 in the SainSmart DDS120 USB oscilloscope.


sainsmart_dds140_powerup.sr
---------------------------

This is the I2C communication during powerup between the Cypress FX2 and the
Microchip 24LC64 in the SainSmart DDS140 USB oscilloscope.