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| author | Matt Ranostay <mranostay@gmail.com> | 2013-03-06 07:40:35 -0800 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2013-03-09 11:44:46 +0100 |
| commit | a26d276427a0af78b2f6a660f34b1c54387c53d7 (patch) | |
| tree | e96584fcadc5ab6143ed79228cf149480c8c62ca /vfd | |
| parent | d7e1285ae4953d0b877cc9ed0603de16f2fde966 (diff) | |
| download | sigrok-dumps-a26d276427a0af78b2f6a660f34b1c54387c53d7.tar.gz sigrok-dumps-a26d276427a0af78b2f6a660f34b1c54387c53d7.zip | |
Fixed up a few rogue tabs in README
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
Diffstat (limited to 'vfd')
| -rw-r--r-- | vfd/max6921/beagleboard_nixie_cape/README | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/vfd/max6921/beagleboard_nixie_cape/README b/vfd/max6921/beagleboard_nixie_cape/README index a71a3fa..f6cd92d 100644 --- a/vfd/max6921/beagleboard_nixie_cape/README +++ b/vfd/max6921/beagleboard_nixie_cape/README @@ -13,12 +13,12 @@ Logic analyzer setup The logic analyzer used was Open Bench Logic Sniffer (at 10Mhz): - Probe MAX6921 Pin + Probe MAX6921 Pin -------------------------- - 0 LOAD - 1 DATA - 2 CLK - 3 BLANK (PWM Brightness Control) + 0 LOAD + 1 DATA + 2 CLK + 3 BLANK (PWM Brightness Control) Data ---- |