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author | Oleksij Rempel <fixed-term.Oleksij.Rempel@de.bosch.com> | 2016-08-01 14:33:07 +0200 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2016-08-22 17:32:01 +0200 |
commit | 86f8acafaf5791cdddd9ede239ab3e4f37b02d9d (patch) | |
tree | 995cd9e6869be5357e40539b0f5b2b95a9ea722a /uart/uni-t_ut-d04_cable/vc820_win_1mA_nosw.sr | |
parent | c2745d1faff57c32d7af8afa54060ba82db4150c (diff) | |
download | sigrok-dumps-86f8acafaf5791cdddd9ede239ab3e4f37b02d9d.tar.gz sigrok-dumps-86f8acafaf5791cdddd9ede239ab3e4f37b02d9d.zip |
Add some ssi32 samples
ssi32_bananapi_loop_test.sr - made with Banana Pi loop test setup
ssi32_watchdog.sr - watchdog ping made on real HW.
Signed-off-by: Oleksij Rempel <fixed-term.Oleksij.Rempel@de.bosch.com>
Diffstat (limited to 'uart/uni-t_ut-d04_cable/vc820_win_1mA_nosw.sr')
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