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author | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-02 18:29:16 +0100 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-02 18:29:16 +0100 |
commit | 38019245370f8202dc9adda58f985ce1a3401002 (patch) | |
tree | 5b7e10780e841b3a46388ab55e66c1f0fcaa496b /spi/allmodes/README | |
parent | 5faa8c0485441a3605f8685b341707c0ef8dcf96 (diff) | |
download | sigrok-dumps-38019245370f8202dc9adda58f985ce1a3401002.tar.gz sigrok-dumps-38019245370f8202dc9adda58f985ce1a3401002.zip |
spi/allmodes: Add dumps with various SPI settings.
Diffstat (limited to 'spi/allmodes/README')
-rw-r--r-- | spi/allmodes/README | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/spi/allmodes/README b/spi/allmodes/README new file mode 100644 index 0000000..027734a --- /dev/null +++ b/spi/allmodes/README @@ -0,0 +1,21 @@ +------------------------------------------------------------------------------- +SPI modes +------------------------------------------------------------------------------- + +This is a set of example captures of some SPI transmissions with various +SPI modes (CPOL/CPHA combinations), CS# polarity settings, word sizes, +LSB-/MSB-first settings, and trigger setups. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a USBee SX (at 16MHz): + + Probe SPI + --------------- + 2 (red) MOSI + 3 (orange) MISO + 4 (yellow) CLK + 5 (green) CS# + |