diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-21 15:07:09 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-21 15:07:09 +0100 |
| commit | 1cd115bfa6b37e5172dfc3687ea9b70b38430c05 (patch) | |
| tree | c19606303b9ebc6f58c4bdab943d67a6061e16bc /random/1mhz_clock/README | |
| parent | 61c463b6f6cd6f79f3b90b74b0dad3a00422c951 (diff) | |
| download | sigrok-dumps-1cd115bfa6b37e5172dfc3687ea9b70b38430c05.tar.gz sigrok-dumps-1cd115bfa6b37e5172dfc3687ea9b70b38430c05.zip | |
Move 1mhz_clock/ into misc/.
Diffstat (limited to 'random/1mhz_clock/README')
| -rw-r--r-- | random/1mhz_clock/README | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/random/1mhz_clock/README b/random/1mhz_clock/README deleted file mode 100644 index a715bca..0000000 --- a/random/1mhz_clock/README +++ /dev/null @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- -1MHz clock signal -------------------------------------------------------------------------------- - -This is a set of example captures of a digital 1MHz clock signal (rectangle -signal) generated using a function generator, sampled using a logic analyzer. - - -Logic analyzer setup --------------------- - -The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): - - Probe Signal - ----------------------------- - 1 1MHz clock signal - - -Data ----- - -The sigrok command line used was: - - sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ - -o <filename> -p XXXX - -XXXX specifies how many probes to sample/save: - - - 1 signal: -p 1 - - 4 signals: -p 1-4 - - 7 signals: -p 1-7 - - 8 signals: -p 1-8 - - 9 signals: -p 1-9 - - 16 signals: -p 1-16 - |