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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-01-02 20:49:26 +0100 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-01-02 20:49:26 +0100 |
| commit | 775d871cb284541de557d1a658c56c0c060c2caa (patch) | |
| tree | 2fe41b5ff4c71f3d5d0fe2161e31b2a73db1b063 /pwm/alsa_test/pwmtest_snippet.sr | |
| parent | 16931eb480ba5df923c1508f3d83719eddcc5ab3 (diff) | |
| download | sigrok-dumps-775d871cb284541de557d1a658c56c0c060c2caa.tar.gz sigrok-dumps-775d871cb284541de557d1a658c56c0c060c2caa.zip | |
misc/vcd: introduce VCD example files with not yet supported features
The VCD input module of the libsigrok library currently exclusively
supports single bit logic data. Provide some captures in the VCD format
which exercise currently unsupported features which a future version of
the input module might want to support (bit vectors, multi bit numbers,
analog signals).
Diffstat (limited to 'pwm/alsa_test/pwmtest_snippet.sr')
0 files changed, 0 insertions, 0 deletions