diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2012-08-09 01:29:40 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2012-08-09 01:35:30 +0200 |
| commit | f83bdf56455663ff614e304ad8feeb99780e642f (patch) | |
| tree | e3d54190c991e227a7cf1602cda88f0fb4c2b4fd /onewire/sockit_owm | |
| parent | d3149842b6d96cfaae1d2164be494ac95fb233a8 (diff) | |
| download | sigrok-dumps-f83bdf56455663ff614e304ad8feeb99780e642f.tar.gz sigrok-dumps-f83bdf56455663ff614e304ad8feeb99780e642f.zip | |
sockit_owm: Cosmetics, typos, formatting.
Diffstat (limited to 'onewire/sockit_owm')
| -rw-r--r-- | onewire/sockit_owm/README | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/onewire/sockit_owm/README b/onewire/sockit_owm/README index ec19be4..c84e364 100644 --- a/onewire/sockit_owm/README +++ b/onewire/sockit_owm/README @@ -1,15 +1,32 @@ -This directory contains waveforms created by accesing various onewire devices +------------------------------------------------------------------------------- +Onewire dumps, sockit_owm master +------------------------------------------------------------------------------- + +This directory contains waveforms created by accessing various onewire devices using the 'sockit_owm' Verilog master. The master is used in a demo hardware (Terasic DE1 development board, and a Quartus/Qsys project) and software (also -available as a Nios II project) implementation available at the next GIT repo. +available as a Nios II project) implementation. +Details: https://github.com/jeras/sockit_owm -This dumps were created using sigrok with the following command: +Logic analyzer setup +-------------------- + +The logic analyzer used was a Saleae Logic (at 8MHz): + + Probe 1-Wire pin + ---------------------- + 1 (black) OWR + + +Data +---- -sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr +The sigrok command line used was: + sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr This is the console output after running the demo: |