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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-21 15:07:09 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-21 15:07:09 +0100 |
| commit | 1cd115bfa6b37e5172dfc3687ea9b70b38430c05 (patch) | |
| tree | c19606303b9ebc6f58c4bdab943d67a6061e16bc /misc | |
| parent | 61c463b6f6cd6f79f3b90b74b0dad3a00422c951 (diff) | |
| download | sigrok-dumps-1cd115bfa6b37e5172dfc3687ea9b70b38430c05.tar.gz sigrok-dumps-1cd115bfa6b37e5172dfc3687ea9b70b38430c05.zip | |
Move 1mhz_clock/ into misc/.
Diffstat (limited to 'misc')
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_16channels.sr | bin | 0 -> 77482 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_1channels.sr | bin | 0 -> 42419 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_4channels.sr | bin | 0 -> 42572 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_7channels.sr | bin | 0 -> 42513 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_8channels.sr | bin | 0 -> 42845 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/1mhz_clock_9channels.sr | bin | 0 -> 77582 bytes | |||
| -rw-r--r-- | misc/1mhz_clock/README | 35 |
7 files changed, 35 insertions, 0 deletions
diff --git a/misc/1mhz_clock/1mhz_clock_16channels.sr b/misc/1mhz_clock/1mhz_clock_16channels.sr Binary files differnew file mode 100644 index 0000000..c9b5965 --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_16channels.sr diff --git a/misc/1mhz_clock/1mhz_clock_1channels.sr b/misc/1mhz_clock/1mhz_clock_1channels.sr Binary files differnew file mode 100644 index 0000000..0fdd10e --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_1channels.sr diff --git a/misc/1mhz_clock/1mhz_clock_4channels.sr b/misc/1mhz_clock/1mhz_clock_4channels.sr Binary files differnew file mode 100644 index 0000000..6cc3e06 --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_4channels.sr diff --git a/misc/1mhz_clock/1mhz_clock_7channels.sr b/misc/1mhz_clock/1mhz_clock_7channels.sr Binary files differnew file mode 100644 index 0000000..0c84367 --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_7channels.sr diff --git a/misc/1mhz_clock/1mhz_clock_8channels.sr b/misc/1mhz_clock/1mhz_clock_8channels.sr Binary files differnew file mode 100644 index 0000000..30f52fc --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_8channels.sr diff --git a/misc/1mhz_clock/1mhz_clock_9channels.sr b/misc/1mhz_clock/1mhz_clock_9channels.sr Binary files differnew file mode 100644 index 0000000..fc7504a --- /dev/null +++ b/misc/1mhz_clock/1mhz_clock_9channels.sr diff --git a/misc/1mhz_clock/README b/misc/1mhz_clock/README new file mode 100644 index 0000000..a715bca --- /dev/null +++ b/misc/1mhz_clock/README @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +1MHz clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a digital 1MHz clock signal (rectangle +signal) generated using a function generator, sampled using a logic analyzer. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): + + Probe Signal + ----------------------------- + 1 1MHz clock signal + + +Data +---- + +The sigrok command line used was: + + sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ + -o <filename> -p XXXX + +XXXX specifies how many probes to sample/save: + + - 1 signal: -p 1 + - 4 signals: -p 1-4 + - 7 signals: -p 1-7 + - 8 signals: -p 1-8 + - 9 signals: -p 1-9 + - 16 signals: -p 1-16 + |