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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2017-08-11 00:36:44 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2017-08-11 00:58:34 +0200 |
| commit | f711de81a725d61c027b45d2fd51efaecb17b4e4 (patch) | |
| tree | e6e2a13a7d7002668bcc2ea5d5d7841bed4bad3e /misc/square_wave_analog | |
| parent | 6bce1e61fa72a8fe82ef64805f8dd53fc9570d9b (diff) | |
| download | sigrok-dumps-f711de81a725d61c027b45d2fd51efaecb17b4e4.tar.gz sigrok-dumps-f711de81a725d61c027b45d2fd51efaecb17b4e4.zip | |
Add a square wave digital + analog capture.
Diffstat (limited to 'misc/square_wave_analog')
| -rw-r--r-- | misc/square_wave_analog/100khz_clock_2logic_1analog.sr | bin | 0 -> 4030 bytes | |||
| -rw-r--r-- | misc/square_wave_analog/README | 19 |
2 files changed, 19 insertions, 0 deletions
diff --git a/misc/square_wave_analog/100khz_clock_2logic_1analog.sr b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr Binary files differnew file mode 100644 index 0000000..670e8bc --- /dev/null +++ b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr diff --git a/misc/square_wave_analog/README b/misc/square_wave_analog/README new file mode 100644 index 0000000..267d41e --- /dev/null +++ b/misc/square_wave_analog/README @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +Analog clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a clock signal (rectangle signal) +generated using a function generator, sampled using an LA/MSO. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Noname LHT00SU1 (at 12MHz): + + Probe Signal + ------------------------------- + 1DCH 100kHz clock signal + 2DCH same 100kHz clock signal + 1ACH same 100kHz clock signal + |