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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2017-05-26 22:22:59 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2017-05-26 22:22:59 +0200 |
| commit | 44fbf09632f47b3dcfe573377ee550ea00c601df (patch) | |
| tree | 246c53a70f692c5966e933bcb2a85607ba0dcd19 /i2c/eeprom_24xx/attiny13_i2c/README | |
| parent | cefb8a228437d78ca18395c8d317d31354f6bfe4 (diff) | |
| download | sigrok-dumps-44fbf09632f47b3dcfe573377ee550ea00c601df.tar.gz sigrok-dumps-44fbf09632f47b3dcfe573377ee550ea00c601df.zip | |
eeprom24xx: Add an ATtiny13 I²C example dump.
Diffstat (limited to 'i2c/eeprom_24xx/attiny13_i2c/README')
| -rw-r--r-- | i2c/eeprom_24xx/attiny13_i2c/README | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/i2c/eeprom_24xx/attiny13_i2c/README b/i2c/eeprom_24xx/attiny13_i2c/README new file mode 100644 index 0000000..afdb957 --- /dev/null +++ b/i2c/eeprom_24xx/attiny13_i2c/README @@ -0,0 +1,32 @@ +------------------------------------------------------------------------------- +Atmel ATtiny13 I²C +------------------------------------------------------------------------------- + +This is a set of example captures of the I²C traffic to/from the Atmel +ATtiny13 chip and the Cypress FX2 in the Braintechnology USB-LPS device. + +Details: +http://www.atmel.com/images/doc2535.pdf +http://www.braintechnology.de/braintechnology/usb_lps.html + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a CWAV USBee SX (at 12MHz): + + Probe ATtiny13 pin + ------------------------ + 0 (black) PB0 + 1 (brown) PB1/SDA + 2 (red) PB2/SCL + 3 (orange) PB3 + 4 (yellow) PB4 + 5 (green) PB5 + + +Data +---- + +The data contains the power-up sequence when the USB cable is attached. + |