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authorUwe Hermann <uwe@hermann-uwe.de>2017-04-09 19:46:16 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2017-04-09 22:42:51 +0200
commitf90bc77c8e8dab616cf4bac5b887d052f8d4f97b (patch)
tree47ccba74b974afa18dd0c3e70d02ba73c56872c2
parent6b4d6289dffb698701defb62486ff67d1c801a28 (diff)
downloadsigrok-dumps-f90bc77c8e8dab616cf4bac5b887d052f8d4f97b.tar.gz
sigrok-dumps-f90bc77c8e8dab616cf4bac5b887d052f8d4f97b.zip
Add a Microchip 24LC64 dump (Instrustar ISDS205A).
-rw-r--r--i2c/eeprom_24xx/microchip_24lc64/README34
-rw-r--r--i2c/eeprom_24xx/microchip_24lc64/instrustar_isds250a_powerup.srbin0 -> 49190 bytes
2 files changed, 34 insertions, 0 deletions
diff --git a/i2c/eeprom_24xx/microchip_24lc64/README b/i2c/eeprom_24xx/microchip_24lc64/README
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--- /dev/null
+++ b/i2c/eeprom_24xx/microchip_24lc64/README
@@ -0,0 +1,34 @@
+-------------------------------------------------------------------------------
+Microchip 24LC64
+-------------------------------------------------------------------------------
+
+This is a set of example captures of Microchip 24LC64 I2C traffic.
+
+Details:
+https://www.microchip.com/wwwproducts/en/24LC64
+http://ww1.microchip.com/downloads/en/DeviceDoc/21189T.pdf
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a CWAV USBee SX or equivalent (at 8MHz):
+
+ Probe I2C pin
+ -------------------
+ 0 (black) SCL
+ 1 (brown) SDA
+
+
+amfpga-cpld-board-fx2-init.sr
+-----------------------------
+
+This is the I2C communication of a Microchip 24LC64 in an AMFPGA CPLD board.
+
+
+instrustar_isds250a_powerup.sr
+------------------------------
+
+This is the I2C communication during powerup between the Cypress FX2 and the
+Microchip 24LC64 in the Instrustar ISDS205A USB oscilloscope.
+
diff --git a/i2c/eeprom_24xx/microchip_24lc64/instrustar_isds250a_powerup.sr b/i2c/eeprom_24xx/microchip_24lc64/instrustar_isds250a_powerup.sr
new file mode 100644
index 0000000..9e97070
--- /dev/null
+++ b/i2c/eeprom_24xx/microchip_24lc64/instrustar_isds250a_powerup.sr
Binary files differ