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| author | Anton Blanchard <anton@ozlabs.org> | 2021-09-13 11:17:07 +1000 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2021-12-21 14:07:22 +0100 |
| commit | 8c42ec4ccab98196fb5ebfeeb3556a26a25ff514 (patch) | |
| tree | bef93b57bb011373caf591e67fbc59f3620d6126 | |
| parent | 4637833ee5f819277483e6ac322accf254c15f6a (diff) | |
| download | sigrok-dumps-8c42ec4ccab98196fb5ebfeeb3556a26a25ff514.tar.gz sigrok-dumps-8c42ec4ccab98196fb5ebfeeb3556a26a25ff514.zip | |
lpc: Add capture from Intel H55 chipsset
This adds an LPC I/O read transaction from an Intel H55 chipset.
[ gsi: rename probes to improve usability ]
| -rw-r--r-- | lpc/h55/README | 30 | ||||
| -rw-r--r-- | lpc/h55/h55_lpc_io_write.sr | bin | 0 -> 570 bytes |
2 files changed, 30 insertions, 0 deletions
diff --git a/lpc/h55/README b/lpc/h55/README new file mode 100644 index 0000000..dba8d95 --- /dev/null +++ b/lpc/h55/README @@ -0,0 +1,30 @@ +------------------------------------------------------------------------------- +Intel H55 LPC (low pin count) traffic +------------------------------------------------------------------------------- + +This capture is an LPC (low pin count) I/O read transaction from an Intel H55 +chipset on a Foxconn H55MXV motherboard. + +Details: +http://en.wikipedia.org/wiki/Low_Pin_Count + + +Hardware setup +-------------- + +The capture was taken with an FPGA sampling at 200 MHz and imported into sigrok +as 8bit binary data. + + Probe LPC + ---------- + 2 LCLK + 3 LFRAME# + 4 LAD0 + 5 LAD1 + 6 LAD2 + 7 LAD3 + + +h55_lpc_io_write.sr +--------------- +An I/O write to 0x2e (super IO index register) of 0x55. diff --git a/lpc/h55/h55_lpc_io_write.sr b/lpc/h55/h55_lpc_io_write.sr Binary files differnew file mode 100644 index 0000000..c4dab93 --- /dev/null +++ b/lpc/h55/h55_lpc_io_write.sr |