1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
|
##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
import sigrokdecode as srd
# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
return (b & 0x0f) + ((b >> 4) * 10)
class Decoder(srd.Decoder):
api_version = 1
id = 'rtc8564'
name = 'RTC-8564'
longname = 'Epson RTC-8564 JE/NB'
desc = 'Realtime clock module protocol.'
license = 'gplv2+'
inputs = ['i2c']
outputs = ['rtc8564']
probes = []
optional_probes = [
{'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
{'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
{'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
]
options = {}
annotations = \
[['reg-0x%02x' % i, 'Register 0x%02x' % i] for i in range(8 + 1)] + [
['read', 'Read date/time'],
['write', 'Write date/time'],
['bit-reserved', 'Reserved bit'],
['bit-vl', 'VL bit'],
['bit-century', 'Century bit'],
['reg-read', 'Register read'],
['reg-write', 'Register write'],
]
annotation_rows = (
('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
('regs', 'Register access', (14, 15)),
('date-time', 'Date/time', (9, 10)),
)
def __init__(self, **kwargs):
self.state = 'IDLE'
self.hours = -1
self.minutes = -1
self.seconds = -1
self.days = -1
self.weekdays = -1
self.months = -1
self.years = -1
self.bits = []
def start(self):
# self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
def putx(self, data):
self.put(self.ss, self.es, self.out_ann, data)
def putd(self, bit1, bit2, data):
self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
def putr(self, bit):
self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
def handle_reg_0x00(self, b): # Control register 1
pass
def handle_reg_0x01(self, b): # Control register 2
ti_tp = 1 if (b & (1 << 4)) else 0
af = 1 if (b & (1 << 3)) else 0
tf = 1 if (b & (1 << 2)) else 0
aie = 1 if (b & (1 << 1)) else 0
tie = 1 if (b & (1 << 0)) else 0
ann = ''
s = 'repeated' if ti_tp else 'single-shot'
ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
'events\n' % (ti_tp, s)
s = '' if af else 'no '
ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
s = '' if tf else 'no '
ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
s = 'enabled' if aie else 'prohibited'
ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
'occurs\n' % (aie, s)
s = 'enabled' if tie else 'prohibited'
ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
'event occurs\n' % (tie, s)
self.putx([1, [ann]])
def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
vl = 1 if (b & (1 << 7)) else 0
self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
'VL: %d' % vl, 'VL']])
s = self.seconds = bcd2int(b & 0x7f)
self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
def handle_reg_0x03(self, b): # Minutes
self.putr(7)
m = self.minutes = bcd2int(b & 0x7f)
self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
def handle_reg_0x04(self, b): # Hours
self.putr(7)
self.putr(6)
h = self.hours = bcd2int(b & 0x3f)
self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
def handle_reg_0x05(self, b): # Days
self.putr(7)
self.putr(6)
d = self.days = bcd2int(b & 0x3f)
self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
def handle_reg_0x06(self, b): # Weekdays
for i in (7, 6, 5, 4, 3):
self.putr(i)
w = self.weekdays = bcd2int(b & 0x07)
self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
def handle_reg_0x07(self, b): # Months / century bit
c = 1 if (b & (1 << 7)) else 0
self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
'Cent: %d' % c, 'C: %d' % c, 'C']])
self.putr(6)
self.putr(5)
m = self.months = bcd2int(b & 0x1f)
self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
def handle_reg_0x08(self, b): # Years
y = self.years = bcd2int(b & 0xff)
self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
def handle_reg_0x09(self, b): # Alarm, minute
pass
def handle_reg_0x0a(self, b): # Alarm, hour
pass
def handle_reg_0x0b(self, b): # Alarm, day
pass
def handle_reg_0x0c(self, b): # Alarm, weekday
pass
def handle_reg_0x0d(self, b): # CLKOUT output
pass
def handle_reg_0x0e(self, b): # Timer setting
pass
def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
pass
def decode(self, ss, es, data):
cmd, databyte = data
# Collect the 'BITS' packet, then return. The next packet is
# guaranteed to belong to these bits we just stored.
if cmd == 'BITS':
self.bits = databyte
return
# Store the start/end samples of this I²C packet.
self.ss, self.es = ss, es
# State machine.
if self.state == 'IDLE':
# Wait for an I²C START condition.
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
self.block_start_sample = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
if cmd != 'ADDRESS WRITE':
return
self.state = 'GET REG ADDR'
elif self.state == 'GET REG ADDR':
# Wait for a data write (master selects the slave register).
if cmd != 'DATA WRITE':
return
self.reg = databyte
self.state = 'WRITE RTC REGS'
elif self.state == 'WRITE RTC REGS':
# If we see a Repeated Start here, it's probably an RTC read.
if cmd == 'START REPEAT':
self.state = 'READ RTC REGS'
return
# Otherwise: Get data bytes until a STOP condition occurs.
if cmd == 'DATA WRITE':
r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
'WR %s' % s, 'WR', 'W']])
handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
handle_reg(databyte)
self.reg += 1
# TODO: Check for NACK!
elif cmd == 'STOP':
# TODO: Handle read/write of only parts of these items.
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
self.put(self.block_start_sample, es, self.out_ann,
[9, ['Write date/time: %s' % d, 'Write: %s' % d,
'W: %s' % d]])
self.state = 'IDLE'
else:
pass # TODO
elif self.state == 'READ RTC REGS':
# Wait for an address read operation.
# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
if cmd == 'ADDRESS READ':
self.state = 'READ RTC REGS2'
return
else:
pass # TODO
elif self.state == 'READ RTC REGS2':
if cmd == 'DATA READ':
r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
'RR %s' % s, 'RR', 'R']])
handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
handle_reg(databyte)
self.reg += 1
# TODO: Check for NACK!
elif cmd == 'STOP':
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
self.put(self.block_start_sample, es, self.out_ann,
[10, ['Read date/time: %s' % d, 'Read: %s' % d,
'R: %s' % d]])
self.state = 'IDLE'
else:
pass # TODO?
else:
raise Exception('Invalid state: %s' % self.state)
|
