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Use the "if not self.samplerate" form, which catches both the case
where self.samplerate is None, as well as the case where it is 0.
This is also consistent with all the other PDs.
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For consistency with other decoders, convert all the double quotes around
strings to single quotes.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
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PID decoding is normally done in the packet layer, but the signalling
layer has to switch behaviour on detection of an PREamble PID.
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If the oldsym is not set to 'J' before entering IDLE state, the SOP
detection will never trigger
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If a packet had any errors, the usb_signalling PD will not send an EOP
but an ERR message. Wait for the next SOP in both cases.
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If a device or host did not receive a handshake 18 bit times after the
EOP, there was a transmission error and the host may repeat the
transmission
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In automatic mode, the bus is assumed to be in IDLE state. After a
RESET, the bus state is checked again.
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Resets are at least 10ms at the root hub downstream facing port and
2.5us at the device (root hub reset may be shortened by itermediate
hubs).
Keep-alive is a low-speed only signalling condition, as low-speed has no
SOFs to inhibit devices to enter suspend
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Instead of centering the block around the sampleposition, which shows
some visual glitches due to rounding, use the edge positions already
known. Remove unused halfbit symbol.
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Only SE0 and J are valid symbols during EOP
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Do not call get_eop() from get_bit(), but directly issue the symbol. As
get_eop() is only called during the GET EOP state, the SE0 is implicit and
there is no need to save it into the syms array.
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More than six consecutive 1's are an error
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No need to replicate the symbol formatting in several places
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Decode and packetize the Biphase Mark Coding (aka differential Manchester)
as used in the Universal Serial Bus Power Delivery Specification Revision 2.0
v1.1, then decode the packet content.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
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(this PD is indeed stacked on top of SPI)
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1. Show Frame Error on the Start bit
2. Don't overwrite framing errors with (valid) start/stop bit info
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The new decoder stacks on top of the usb_packet PD. It adds one new
annotation row, and is able to save the decoded data as PCAP trace.
It has been successfully tested against all traces in sigrok-dumps and
some more traces.
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USB low/full speed allows for frequency tolerance of 1.5%/0.25%. At
maximum packet size (sync + PID + data + CRC16) of 12 bytes/1027 bytes
this amounts to 1.4 bits/20 bits, so the decoder has to lock to the
actual symbol frequency to avoid any symbol misdetections.
The signal is sampled twice, once at the symbol center and once at
the expected edge position. Comparing the symbol at both positions gives
an indication if the current bit width is too low or too high. Adjust
accordingly.
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In case CRC validation fails, an crc5-err/crc16-err annotation is issued,
instead of crc5-ok/crc16-ok, and the error is noted in the annotation
text.
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There is a small typo in the rfm12 protocol decoder that I just noticed:
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It seems the Python we ship along our Windows binaries does not
support u"..." strings, even though it's been a language feature
since Python 2. Remove the "u" prefix to avoid a syntax error.
Also, consistently use format "%.1f" at all scales.
This fixes bug #569.
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The STM32F10xxx has two serially connected JTAG TAPs, the boundary scan tap
(5 bits) and the Cortex-M3 TAP (4 bits). See UM 31.5 "STM32F10xxx JTAG TAP
connection" for details.
Due to this, we need to ignore the last bit of each data shift (and we
currently ignore the 5 bits of the boundary scan tap).
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The code was previously not decoding a bit for the first state change
to SHIFT-IR/-DR, which was incorrect.
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The buttons are pressed if the respective bit is 0.
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Instead of showing raw values in the annotations, calculate the
actual voltage (based on raw value, gain, and Vref) and use that.
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- If LOAD goes low *and* LDAC is already low, the voltage is set
immediately.
- If LOAD goes low but LDAC is high, the value is only written into
an internal register, but the voltage is not changed (yet).
- If LDAC goes low, all four DAC voltages (DAC A/B/C/D) are set
according to the respective register values at the same time.
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