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The STM32F10xxx has two serially connected JTAG TAPs, the boundary scan tap
(5 bits) and the Cortex-M3 TAP (4 bits). See UM 31.5 "STM32F10xxx JTAG TAP
connection" for details.
Due to this, we need to ignore the last bit of each data shift (and we
currently ignore the 5 bits of the boundary scan tap).
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The code was previously not decoding a bit for the first state change
to SHIFT-IR/-DR, which was incorrect.
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The buttons are pressed if the respective bit is 0.
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Instead of showing raw values in the annotations, calculate the
actual voltage (based on raw value, gain, and Vref) and use that.
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- If LOAD goes low *and* LDAC is already low, the voltage is set
immediately.
- If LOAD goes low but LDAC is high, the value is only written into
an internal register, but the voltage is not changed (yet).
- If LDAC goes low, all four DAC voltages (DAC A/B/C/D) are set
according to the respective register values at the same time.
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Previously the PD was blindly trying to decode any packet, no matter
whether it was too short (and/or bogus) or not, causing issues like this:
srd: Calling usb_packet decode(): IndexError: list index out of range
Such cases of invalid input are now handled better by emitting "UNKNOWN"
and "Invalid packet" annotations.
This fixes bug #186.
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Thanks to Pavel Sukortsev for the bug report and fix.
This fixes bug #623.
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In the current state the decoder can decode the following commands:
CMD0, CMD2, CMD3, CMD6, CMD7, CMD8, CMD9, CMD10, CMD13, CMD16, CMD55,
ACMD6, ACMD13, ACMD41, ACMD51.
Other commands (and more details for existing commands) will be added later.
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No interpretation of register bits, nor attempting to decode packet contents,
but all shifted register addresses and long register memory regions are
decoded.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Decodes reads/writes of registers. Understands resetting on chip select if
provided. Does not understand burst mode.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
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Include their compatibility in the dropdown options too.
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This is in preparation of making the PD more generic so it can support
a lot more xx25 series SPI (NOR) flash chips.
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The code was trying to emit annotations before
self.register(srd.OUTPUT_ANN) was run.
This fixes bug #357.
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Avoid decoding and outputting data from the SPI bus if the CS pin
hasn't been asserted. This avoids confusing both users and stacked
decoders which otherwise end up seeing traffic intended for other
chips (or just noise).
Note: The old behavior of decoding all traffic is still in place if
no CS pin has been wired up to the decoder.
This fixes bug #559.
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Fixed:
- wrong address decoding for some branches
- error in annotation lists for exception entry/exit
- exception was being thrown for 0E0N p-header packets
- fixes to objdump output parsing, better function name & source code matching
New features:
- added decoding of IRQ names for branch exception info
- added support for -C option to objdump to decode C++ symbol names
- put branches on the "Exceptions" annotation row when they contain exception info.
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This allows for easily extending the PD to support other clones or
compatibles of the nRF24L01(+) chip as well.
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At 3 samples per bit, the uart decoder took the value at the last sample
instead of the middle one. Improve calculations so that sampling is more
accurate at odd number of samples per bit.
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This fixes bug #424.
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This also outputs one item of OUT_BINARY per jitter value (not one
item per ASCII character in the ASCII floating point number).
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
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