diff options
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/arm_itm/__init__.py | 2 | ||||
| -rw-r--r-- | decoders/midi/pd.py | 2 | ||||
| -rw-r--r-- | decoders/qi/pd.py | 2 | ||||
| -rw-r--r-- | decoders/tca6408a/pd.py | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/decoders/arm_itm/__init__.py b/decoders/arm_itm/__init__.py index 3529c2c..1733d36 100644 --- a/decoders/arm_itm/__init__.py +++ b/decoders/arm_itm/__init__.py @@ -18,7 +18,7 @@ ## ''' -This decoder stacks on top of the 'uart' or 'arm_tpiu' PD and decodes the +This decoder stacks on top of the 'uart' or 'arm_tpiu' PD and decodes the ARM Cortex-M processor trace data from Instrumentation Trace Macroblock. ''' diff --git a/decoders/midi/pd.py b/decoders/midi/pd.py index 99b63b0..21c4024 100644 --- a/decoders/midi/pd.py +++ b/decoders/midi/pd.py @@ -2,7 +2,7 @@ ## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2013-2016 Uwe Hermann <uwe@hermann-uwe.de> -## Copyright (C) 2016 Chris Dreher <chrisdreher@hotmail.com> +## Copyright (C) 2016 Chris Dreher <chrisdreher@hotmail.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/decoders/qi/pd.py b/decoders/qi/pd.py index 9782ee5..0c880dd 100644 --- a/decoders/qi/pd.py +++ b/decoders/qi/pd.py @@ -146,7 +146,7 @@ class Decoder(srd.Decoder): 'C: PC = %d MP = %d P = %d C = %d WS = %d WO = %d' % (powerclass, maxpower, prop, count, winsize, winoff), 'Configuration', 'C']) - elif self.packet[0] == 0x71: # Identification + elif self.packet[0] == 0x71: # Identification version = '%d.%d' % ((self.packet[1] & 0xf0) >> 4, self.packet[1] & 0x0f) mancode = '%02x%02x' % (self.packet[2], self.packet[3]) devid = '%02x%02x%02x%02x' % (self.packet[4] & ~0x80, diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 6d4be72..9fa9d23 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -91,7 +91,7 @@ class Decoder(srd.Decoder): return self.state = 'GET SLAVE ADDR' elif self.state == 'GET SLAVE ADDR': - self.chip = databyte + self.chip = databyte self.state = 'GET REG ADDR' elif self.state == 'GET REG ADDR': # Wait for a data write (master selects the slave register). |