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-rw-r--r--decoders/tlc5620/pd.py17
1 files changed, 16 insertions, 1 deletions
diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 0f9b2a1..e086c4d 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -54,6 +54,7 @@ class Decoder(srd.Decoder):
('reg-write', 'Register write'),
('voltage-update', 'Voltage update'),
('voltage-update-all', 'Voltage update (all DACs)'),
+ ('invalid-cmd', 'Invalid command'),
)
annotation_rows = (
('bits', 'Bits', (5,)),
@@ -61,6 +62,7 @@ class Decoder(srd.Decoder):
('registers', 'Registers', (6, 7)),
('voltage-updates', 'Voltage updates', (8,)),
('events', 'Events', (3, 4)),
+ ('errors', 'Errors', (9,)),
)
def __init__(self, **kwargs):
@@ -81,6 +83,16 @@ class Decoder(srd.Decoder):
if len(self.bits) > 11:
self.bits = self.bits[-11:]
+ # If there are less than 11 bits, something is probably wrong.
+ if len(self.bits) < 11:
+ ss, es = self.samplenum, self.samplenum
+ if len(self.bits) >= 2:
+ ss = self.bits[0][1]
+ es = self.bits[-1][1] + (self.bits[1][1] - self.bits[0][1])
+ self.put(ss, es, self.out_ann, [9, ['Command too short']])
+ self.bits = []
+ return False
+
self.ss_dac = self.bits[0][1]
self.es_dac = self.ss_gain = self.bits[2][1]
self.es_gain = self.ss_value = self.bits[3][1]
@@ -115,8 +127,11 @@ class Decoder(srd.Decoder):
self.bits = []
+ return True
+
def handle_falling_edge_load(self):
- self.handle_11bits()
+ if not self.handle_11bits():
+ return
s, v, g = self.dac_select, self.dac_value, self.gain
self.put(self.samplenum, self.samplenum, self.out_ann,
[3, ['Falling edge on LOAD', 'LOAD fall', 'F']])