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-rw-r--r--decoders/st25r39xx_spi/pd.py61
1 files changed, 29 insertions, 32 deletions
diff --git a/decoders/st25r39xx_spi/pd.py b/decoders/st25r39xx_spi/pd.py
index 714fdbc..1b0df07 100644
--- a/decoders/st25r39xx_spi/pd.py
+++ b/decoders/st25r39xx_spi/pd.py
@@ -16,9 +16,6 @@
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
-## v0.1 - 17 September 2019 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 1 (January 2019)
-## v0.2 - 28 April 2020 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 2 (December 2019) https://www.st.com/resource/en/datasheet/st25r3916.pdf
-## v0.3 - 17 June 2020 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 3 (04 June 2020) https://www.st.com/resource/en/datasheet/st25r3916.pdf
import sigrokdecode as srd
from collections import namedtuple
@@ -35,13 +32,13 @@ Data = namedtuple('Data', ['mosi', 'miso'])
class Decoder(srd.Decoder):
api_version = 3
id = 'st25r39xx_spi'
- name = 'ST25R39xx'
+ name = 'ST25R39xx (SPI mode)'
longname = 'STMicroelectronics ST25R39xx'
- desc = 'High performance NFC universal device and EMVCo reader.'
+ desc = 'High performance NFC universal device and EMVCo reader protocol.'
license = 'gplv2+'
inputs = ['spi']
outputs = []
- tags = ['IC', 'Wireless/RF', 'NFC']
+ tags = ['IC', 'Wireless/RF']
annotations = (
('Read', 'Burst register read'),
('Write', 'Burst register write'),
@@ -56,7 +53,7 @@ class Decoder(srd.Decoder):
('warning', 'Warning'),
)
annotation_rows = (
- ('reg', 'Regs', (Ann.prefixes('BURST_'))),
+ ('regs', 'Regs', (Ann.prefixes('BURST_'))),
('cmds', 'Commands', (Ann.DIRECTCMD,)),
('data', 'Data', (Ann.prefixes('FIFO_'))),
('status', 'Status register', (Ann.STATUS,)),
@@ -116,7 +113,7 @@ class Decoder(srd.Decoder):
the decoding of the following data bytes.'''
c = self.parse_command(b)
if c is None:
- self.warn(pos, 'unknown command')
+ self.warn(pos, 'Unknown command')
return
self.cmd, self.dat, self.min, self.max = c
@@ -133,7 +130,7 @@ class Decoder(srd.Decoder):
if self.cmd in ('Write', 'Read', 'WriteB', 'ReadB', 'WriteT', 'ReadT', 'FIFO Write', 'FIFO Read'):
return self.cmd
if self.cmd == 'Cmd':
- reg = dir_cmd.get(self.dat, 'unknown direct command')
+ reg = dir_cmd.get(self.dat, 'Unknown direct command')
return '{} {}'.format(self.cmd, reg)
else:
return 'TODO Cmd {}'.format(self.cmd)
@@ -154,7 +151,7 @@ class Decoder(srd.Decoder):
if (b & 0xC0) == 0x40:
return ('ReadB', addr, 1, 99999)
else:
- self.warn(pos, 'unknown address/command combination')
+ self.warn(pos, 'Unknown address/command combination')
# previous command was 'TestAccess'
elif self.cmd == 'TestAccess':
if (b & 0xC0) == 0x00:
@@ -162,28 +159,28 @@ class Decoder(srd.Decoder):
if (b & 0xC0) == 0x40:
return ('ReadT', addr, 1, 99999)
else:
- self.warn(pos, 'unknown address/command combination')
+ self.warn(pos, 'Unknown address/command combination')
else:
# Space A regs or other operation modes (except Space B)
- # Register Write 0b00xxxxxx 0x00 to 0x3F => 'Write'
- # Register Read 0b01xxxxxx 0x40 to 0x7F => 'Read'
+ # Register Write 0b00xxxxxx 0x00 to 0x3F => 'Write'
+ # Register Read 0b01xxxxxx 0x40 to 0x7F => 'Read'
if (b <= 0x7F):
if (b & 0xC0) == 0x00:
return ('Write', addr, 1, 99999)
if (b & 0xC0) == 0x40:
return ('Read', addr, 1, 99999)
else:
- self.warn(pos, 'unknown address/command combination')
+ self.warn(pos, 'Unknown address/command combination')
else:
- # FIFO Load 0b10000000 0x80 => 'FIFO Write'
- # PT_memory loadA-config 0b10100000 0xA0 => 'Write'
- # PT_memory loadF-config 0b10101000 0xA8 => 'Write'
- # PT_memory loadTSN data 0b10101100 0xAC => 'Write'
- # PT_memory Read 0b10111111 0xBF => 'Read'
- # FIFO Read 0b10011111 0x9F => 'FIFO Read'
- # Direct Command 0b11xxx1xx 0xC0 to 0xE8 => 'Cmd'
- # Register Space-B Access 0b11111011 0xFB => 'Space B'
- # Register Test Access 0b11111100 0xFC => 'TestAccess'
+ # FIFO Load 0b10000000 0x80 => 'FIFO Write'
+ # PT_memory loadA-config 0b10100000 0xA0 => 'Write'
+ # PT_memory loadF-config 0b10101000 0xA8 => 'Write'
+ # PT_memory loadTSN data 0b10101100 0xAC => 'Write'
+ # PT_memory Read 0b10111111 0xBF => 'Read'
+ # FIFO Read 0b10011111 0x9F => 'FIFO Read'
+ # Direct Command 0b11xxx1xx 0xC0 to 0xE8 => 'Cmd'
+ # Register Space-B Access 0b11111011 0xFB => 'Space B'
+ # Register Test Access 0b11111100 0xFC => 'TestAccess'
if b == 0x80:
return ('FIFO Write', b, 1, 99999)
if b == 0xA0:
@@ -203,7 +200,7 @@ class Decoder(srd.Decoder):
if b == 0xFC:
return ('TestAccess', b, 0, 0)
else:
- self.warn(pos, 'unknown address/command combination')
+ self.warn(pos, 'Unknown address/command combination')
def decode_reg(self, pos, ann, regid, data):
'''Decodes a register.
@@ -219,19 +216,19 @@ class Decoder(srd.Decoder):
elif (ann == Ann.BURST_READB) or (ann == Ann.BURST_WRITEB):
# Get the name of the register.
if regid not in regsSpaceB:
- self.warn(pos, 'unknown register SpaceB')
+ self.warn(pos, 'Unknown register SpaceB')
return
name = '{} ({:02X})'.format(regsSpaceB[regid], regid)
elif (ann == Ann.BURST_READT) or (ann == Ann.BURST_WRITET):
# Get the name of the register.
if regid not in regsTest:
- self.warn(pos, 'unknown register Test')
+ self.warn(pos, 'Unknown register Test')
return
name = '{} ({:02X})'.format(regsTest[regid], regid)
else:
# Get the name of the register.
if regid not in regsSpaceA:
- self.warn(pos, 'unknown register SpaceA')
+ self.warn(pos, 'Unknown register SpaceA')
return
name = '{} ({:02X})'.format(regsSpaceA[regid], regid)
else:
@@ -283,7 +280,7 @@ class Decoder(srd.Decoder):
elif self.cmd == 'Cmd':
self.decode_reg(pos, Ann.DIRECTCMD, self.dat, self.mosi_bytes())
else:
- self.warn(pos, 'unhandled command')
+ self.warn(pos, 'Unhandled command {}'.format(self.cmd))
def decode(self, ss, es, data):
if not self.requirements_met:
@@ -306,7 +303,7 @@ class Decoder(srd.Decoder):
# Check if we got the minimum number of data bytes
# after the command byte.
if len(self.mb) < self.min:
- self.warn((ss, ss), 'missing data bytes')
+ self.warn((ss, ss), 'Missing data bytes')
elif self.mb:
self.finish_command(Pos(self.ss_mb, self.es_mb))
@@ -322,14 +319,14 @@ class Decoder(srd.Decoder):
raise ChannelError('Both MISO and MOSI pins are required.')
if self.first:
- # Register Space-B Access 0b11111011 0xFB => 'Space B'
+ # Register Space-B Access 0b11111011 0xFB => 'Space B'
if mosi == 0xFB:
self.first = True
# First MOSI byte 'Space B' command.
self.decode_command(pos, mosi)
# First MISO byte is always the status register.
#self.decode_reg(pos, ANN_STATUS, 'STATUS', [miso])
- # Register TestAccess Access 0b11111100 0xFC => 'TestAccess'
+ # Register TestAccess Access 0b11111100 0xFC => 'TestAccess'
elif mosi == 0xFC:
self.first = True
# First MOSI byte 'TestAccess' command.
@@ -344,7 +341,7 @@ class Decoder(srd.Decoder):
#self.decode_reg(pos, ANN_STATUS, 'STATUS', [miso])
else:
if not self.cmd or len(self.mb) >= self.max:
- self.warn(pos, 'excess byte')
+ self.warn(pos, 'Excess byte')
else:
# Collect the bytes after the command byte.
if self.ss_mb == -1:
generated by cgit v1.2.3-70-g09d2 (git 2.47.0) at 2024-11-15 02:35:00 +0000