diff options
Diffstat (limited to 'decoders/can')
| -rw-r--r-- | decoders/can/pd.py | 65 |
1 files changed, 31 insertions, 34 deletions
diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 45b7a18..9bcbca5 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> +## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -58,6 +58,9 @@ class Decoder(srd.Decoder): def report(self): pass + def putx(self, data): + self.put(self.samplenum, self.samplenum, self.out_ann, data) + def reset_variables(self): self.state = 'IDLE' self.sof = self.frame_type = self.dlc = None @@ -81,7 +84,7 @@ class Decoder(srd.Decoder): return False # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. - self.put(0, 0, self.out_ann, [0, ['Stuff bit: %d' % self.rawbits[-1]]]) + self.putx([0, ['Stuff bit: %d' % self.rawbits[-1]]]) self.bits.pop() # Drop last bit. return True @@ -104,27 +107,27 @@ class Decoder(srd.Decoder): x = self.last_databit + 1 crc_bits = self.bits[x:x + 15 + 1] self.crc = int(''.join(str(d) for d in crc_bits), 2) - self.put(0, 0, self.out_ann, [0, ['CRC: 0x%04x' % self.crc]]) + self.putx([0, ['CRC: 0x%04x' % self.crc]]) if not self.is_valid_crc(crc_bits): - self.put(0, 0, self.out_ann, [0, ['CRC is invalid']]) + self.putx([0, ['CRC is invalid']]) # CRC delimiter bit (recessive) elif bitnum == (self.last_databit + 16): - self.put(0, 0, self.out_ann, [0, ['CRC delimiter: %d' % can_rx]]) + self.putx([0, ['CRC delimiter: %d' % can_rx]]) # ACK slot bit (dominant: ACK, recessive: NACK) elif bitnum == (self.last_databit + 17): ack = 'ACK' if can_rx == 0 else 'NACK' - self.put(0, 0, self.out_ann, [0, ['ACK slot: %s' % ack]]) + self.putx([0, ['ACK slot: %s' % ack]]) # ACK delimiter bit (recessive) elif bitnum == (self.last_databit + 18): - self.put(0, 0, self.out_ann, [0, ['ACK delimiter: %d' % can_rx]]) + self.putx([0, ['ACK delimiter: %d' % can_rx]]) # End of frame (EOF), 7 recessive bits elif bitnum == (self.last_databit + 25): - self.put(0, 0, self.out_ann, [0, ['End of frame', 'EOF']]) + self.putx([0, ['End of frame', 'EOF']]) self.reset_variables() return True @@ -136,18 +139,18 @@ class Decoder(srd.Decoder): # Bit 14: RB0 (reserved bit) # Has to be sent dominant, but receivers should accept recessive too. if bitnum == 14: - self.put(0, 0, self.out_ann, [0, ['RB0: %d' % can_rx]]) + self.putx([0, ['RB0: %d' % can_rx]]) # Bit 12: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. rtr = 'remote' if self.bits[12] == 1 else 'data' - self.put(0, 0, self.out_ann, [0, ['RTR: %s frame' % rtr]]) + self.putx([0, ['RTR: %s frame' % rtr]]) # Bits 15-18: Data length code (DLC), in number of bytes (0-8). elif bitnum == 18: self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) - self.put(0, 0, self.out_ann, [0, ['DLC: %d' % self.dlc]]) + self.putx([0, ['DLC: %d' % self.dlc]]) self.last_databit = 18 + (self.dlc * 8) # Bits 19-X: Data field (0-8 bytes, depending on DLC) @@ -156,8 +159,7 @@ class Decoder(srd.Decoder): for i in range(self.dlc): x = 18 + (8 * i) + 1 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) - self.put(0, 0, self.out_ann, - [0, ['Data byte %d: 0x%02x' % (i, b)]]) + self.putx([0, ['Data byte %d: 0x%02x' % (i, b)]]) elif bitnum > self.last_databit: return self.decode_frame_end(can_rx, bitnum) @@ -170,35 +172,33 @@ class Decoder(srd.Decoder): # Bits 14-31: Extended identifier (EID[17..0]) if bitnum == 31: self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) - self.put(0, 0, self.out_ann, - [0, ['Extended ID: %d (0x%x)' % (self.eid, self.eid)]]) + self.putx([0, ['Extended ID: %d (0x%x)' % (self.eid, self.eid)]]) self.fullid = self.id << 18 | self.eid - self.put(0, 0, self.out_ann, - [0, ['Full ID: %d (0x%x)' % (self.fullid, self.fullid)]]) + self.putx([0, ['Full ID: %d (0x%x)' % (self.fullid, self.fullid)]]) # Bit 12: Substitute remote request (SRR) bit - self.put(0, 0, self.out_ann, [0, ['SRR: %d' % self.bits[12]]]) + self.putx([0, ['SRR: %d' % self.bits[12]]]) # Bit 32: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. if bitnum == 32: rtr = 'remote' if can_rx == 1 else 'data' - self.put(0, 0, self.out_ann, [0, ['RTR: %s frame' % rtr]]) + self.putx([0, ['RTR: %s frame' % rtr]]) # Bit 33: RB1 (reserved bit) elif bitnum == 33: - self.put(0, 0, self.out_ann, [0, ['RB1: %d' % can_rx]]) + self.putx([0, ['RB1: %d' % can_rx]]) # Bit 34: RB0 (reserved bit) elif bitnum == 34: - self.put(0, 0, self.out_ann, [0, ['RB0: %d' % can_rx]]) + self.putx([0, ['RB0: %d' % can_rx]]) # Bits 35-38: Data length code (DLC), in number of bytes (0-8). elif bitnum == 38: self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) - self.put(0, 0, self.out_ann, [0, ['DLC: %d' % self.dlc]]) + self.putx([0, ['DLC: %d' % self.dlc]]) self.last_databit = 38 + (self.dlc * 8) # Bits 39-X: Data field (0-8 bytes, depending on DLC) @@ -207,8 +207,7 @@ class Decoder(srd.Decoder): for i in range(self.dlc): x = 38 + (8 * i) + 1 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) - self.put(0, 0, self.out_ann, - [0, ['Data byte %d: 0x%02x' % (i, b)]]) + self.putx([0, ['Data byte %d: 0x%02x' % (i, b)]]) elif bitnum > self.last_databit: return self.decode_frame_end(can_rx, bitnum) @@ -223,8 +222,8 @@ class Decoder(srd.Decoder): bitnum = len(self.bits) - 1 # For debugging. - # self.put(0, 0, self.out_ann, [0, ['Bit %d (CAN bit %d): %d' % \ - # (self.curbit, bitnum, can_rx)]]) + # self.putx([0, ['Bit %d (CAN bit %d): %d' % \ + # (self.curbit, bitnum, can_rx)]]) # If this is a stuff bit, remove it from self.bits and ignore it. if self.is_stuff_bit(): @@ -234,28 +233,26 @@ class Decoder(srd.Decoder): # Bit 0: Start of frame (SOF) bit if bitnum == 0: if can_rx == 0: - self.put(0, 0, self.out_ann, [0, ['Start of frame', 'SOF']]) + self.putx([0, ['Start of frame', 'SOF']]) else: - self.put(0, 0, self.out_ann, - [1, ['Start of frame (SOF) must be a dominant bit']]) + self.putx([1, ['Start of frame (SOF) must be a dominant bit']]) # Bits 1-11: Identifier (ID[10..0]) # The bits ID[10..4] must NOT be all recessive. elif bitnum == 11: self.id = int(''.join(str(d) for d in self.bits[1:]), 2) - self.put(0, 0, self.out_ann, - [0, ['ID: %d (0x%x)' % (self.id, self.id)]]) + self.putx([0, ['ID: %d (0x%x)' % (self.id, self.id)]]) # RTR or SRR bit, depending on frame type (gets handled later). elif bitnum == 12: - # self.put(0, 0, self.out_ann, [0, ['RTR/SRR: %d' % can_rx]]) + # self.putx([0, ['RTR/SRR: %d' % can_rx]]) pass # Bit 13: Identifier extension (IDE) bit # Standard frame: dominant, extended frame: recessive elif bitnum == 13: ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' - self.put(0, 0, self.out_ann, [0, ['IDE: %s frame' % ide]]) + self.putx([0, ['IDE: %s frame' % ide]]) # Bits 14-X: Frame-type dependent, passed to the resp. handlers. elif bitnum >= 14: @@ -284,7 +281,7 @@ class Decoder(srd.Decoder): if can_rx == 1: continue self.sof = self.samplenum - # self.put(self.sof, self.sof, self.out_ann, [0, ['SOF']]) + # self.putx([0, ['SOF']]) self.state = 'GET BITS' elif self.state == 'GET BITS': # Wait until we're in the correct bit/sampling position. |