summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--decoders/i2c.py5
-rw-r--r--decoders/uart.py25
2 files changed, 13 insertions, 17 deletions
diff --git a/decoders/i2c.py b/decoders/i2c.py
index cfaacb0..b0273c0 100644
--- a/decoders/i2c.py
+++ b/decoders/i2c.py
@@ -133,7 +133,7 @@ class Decoder(srd.Decoder):
{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
]
options = {
- 'address-space': ['Address space (in bits)', 7],
+ 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
}
annotations = [
# ANN_SHIFTED
@@ -157,6 +157,9 @@ class Decoder(srd.Decoder):
self.oldscl = None
self.oldsda = None
+ # Set protocol decoder option defaults.
+ self.addressing = Decoder.options['addressing'][1]
+
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
diff --git a/decoders/uart.py b/decoders/uart.py
index f0f3bf8..a72578f 100644
--- a/decoders/uart.py
+++ b/decoders/uart.py
@@ -215,7 +215,6 @@ class Decoder(srd.Decoder):
'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
'bit_order': ['Bit order', LSB_FIRST],
# TODO: Options to invert the signal(s).
- # ...
}
annotations = [
# ANN_ASCII
@@ -231,14 +230,6 @@ class Decoder(srd.Decoder):
]
def __init__(self, **kwargs):
- # Set defaults, can be overridden in 'start'.
- self.baudrate = 115200
- self.num_data_bits = 8
- self.parity = PARITY_NONE
- self.check_parity = True
- self.num_stop_bits = 1
- self.bit_order = LSB_FIRST
-
self.samplenum = 0
self.frame_start = -1
self.startbit = -1
@@ -253,18 +244,20 @@ class Decoder(srd.Decoder):
self.oldrx = None
self.oldtx = None
+ # Set protocol decoder option defaults.
+ self.baudrate = Decoder.options['baudrate'][1]
+ self.num_data_bits = Decoder.options['num_data_bits'][1]
+ self.parity = Decoder.options['parity'][1]
+ self.check_parity = Decoder.options['parity_check'][1]
+ self.num_stop_bits = Decoder.options['num_stop_bits'][1]
+ self.bit_order = Decoder.options['bit_order'][1]
+
def start(self, metadata):
self.samplerate = metadata['samplerate']
self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
- # TODO
- ### self.baudrate = metadata['baudrate']
- ### self.num_data_bits = metadata['num_data_bits']
- ### self.parity = metadata['parity']
- ### self.parity_check = metadata['parity_check']
- ### self.num_stop_bits = metadata['num_stop_bits']
- ### self.bit_order = metadata['bit_order']
+ # TODO: Override PD options, if user wants that.
# The width of one UART bit in number of samples.
self.bit_width = float(self.samplerate) / float(self.baudrate)