diff options
| -rw-r--r-- | decoders/pca9571/pd.py | 21 | ||||
| -rw-r--r-- | decoders/tca6408a/pd.py | 18 |
2 files changed, 28 insertions, 11 deletions
diff --git a/decoders/pca9571/pd.py b/decoders/pca9571/pd.py index 8531081..af0ad2d 100644 --- a/decoders/pca9571/pd.py +++ b/decoders/pca9571/pd.py @@ -23,7 +23,7 @@ NUM_OUTPUT_CHANNELS = 8 # TODO: Other I²C functions: general call / reset address, device ID address. -def logic_channels(num_channels, samplerate): +def logic_channels(num_channels): l = [] for i in range(num_channels): l.append(tuple(['p%d' % i, 'P%d' % i])) @@ -55,9 +55,13 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' - self.ss_logic = -1 self.last_write = 0xFF # Chip port default state is high. + self.logic_es = 1 + self.logic_data = [] + for i in range(NUM_OUTPUT_CHANNELS): + self.logic_data.append(bytes([1])) + def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) @@ -65,8 +69,11 @@ class Decoder(srd.Decoder): def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) - def putl(self, data): - self.put(self.ss_logic, self.ss_logic, self.out_logic, data) + def put_logic_states(self): + if (self.es > self.logic_es): + for i in range(NUM_OUTPUT_CHANNELS): + self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) + self.logic_es = self.es def handle_io(self, b): if self.state == 'READ DATA': @@ -79,10 +86,10 @@ class Decoder(srd.Decoder): self.last_write = b self.putx([1, [operation[0] + ': %02X' % b, operation[1] + ': %02X' % b]]) - self.ss_logic = self.ss + for i in range(NUM_OUTPUT_CHANNELS): bit = (b & (1 << i)) != 0 - self.putl([i, bytes([bit])]) + self.logic_data[i] = bytes([bit]) def check_correct_chip(self, addr): if addr != 0x25: @@ -95,6 +102,8 @@ class Decoder(srd.Decoder): cmd, databyte = data self.ss, self.es = ss, es + self.put_logic_states() + # State machine. if cmd in ('ACK', 'BITS'): # Discard 'ACK' and 'BITS'. pass diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index fdfebed..01c4e6d 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -56,7 +56,11 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' self.chip = -1 - self.ss_logic = -1 + + self.logic_es = 1 + self.logic_data = [] + for i in range(NUM_OUTPUT_CHANNELS): + self.logic_data.append(bytes([1])) def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -65,8 +69,11 @@ class Decoder(srd.Decoder): def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) - def putl(self, data): - self.put(self.ss_logic, self.ss_logic, self.out_logic, data) + def put_logic_states(self): + if (self.es > self.logic_es): + for i in range(NUM_OUTPUT_CHANNELS): + self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) + self.logic_es = self.es def handle_reg_0x00(self, b): self.putx([1, ['State of inputs: %02X' % b]]) @@ -74,10 +81,9 @@ class Decoder(srd.Decoder): def handle_reg_0x01(self, b): self.putx([1, ['Outputs set: %02X' % b]]) - self.ss_logic = self.ss for i in range(NUM_OUTPUT_CHANNELS): bit = (b & (1 << i)) != 0 - self.putl([i, bytes([bit])]) + self.logic_data[i] = bytes([bit]) def handle_reg_0x02(self, b): self.putx([1, ['Polarity inverted: %02X' % b]]) @@ -107,6 +113,8 @@ class Decoder(srd.Decoder): # Store the start/end samples of this I²C packet. self.ss, self.es = ss, es + self.put_logic_states() + # State machine. if self.state == 'IDLE': # Wait for an I²C START condition. |