diff options
| -rw-r--r-- | decoders/usb_signalling/pd.py | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index 0ad8fdc..c0e0141 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -100,7 +100,7 @@ class SamplerateError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'usb_signalling' name = 'USB signalling' longname = 'Universal Serial Bus (LS/FS) signalling' @@ -145,11 +145,10 @@ class Decoder(srd.Decoder): self.samplenum_target = None self.samplenum_edge = None self.samplenum_lastedge = 0 - self.oldpins = None self.edgepins = None self.consecutive_ones = 0 self.bits = None - self.state = 'INIT' + self.state = 'IDLE' def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -298,17 +297,21 @@ class Decoder(srd.Decoder): self.oldsym = 'J' self.state = 'IDLE' - def decode(self, ss, es, data): + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - for (self.samplenum, pins) in data: + + # Seed internal state from the very first sample. + pins = self.wait({'skip': 1}) + sym = symbols[self.options['signalling']][pins] + self.handle_idle(sym) + + while True: # State machine. if self.state == 'IDLE': - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins = pins - sym = symbols[self.signalling][tuple(pins)] + # Wait for any edge on either DP and/or DM. + pins = self.wait([{0: 'e'}, {1: 'e'}]) + sym = symbols[self.signalling][pins] if sym == 'SE0': self.samplenum_lastedge = self.samplenum self.state = 'WAIT IDLE' @@ -317,28 +320,22 @@ class Decoder(srd.Decoder): self.edgepins = pins elif self.state in ('GET BIT', 'GET EOP'): # Wait until we're in the middle of the desired bit. - if self.samplenum == self.samplenum_edge: - self.edgepins = pins - if self.samplenum < self.samplenum_target: - continue - sym = symbols[self.signalling][tuple(pins)] + self.edgepins = self.wait([{'skip': self.samplenum_edge - self.samplenum}]) + pins = self.wait([{'skip': self.samplenum_target - self.samplenum}]) + + sym = symbols[self.signalling][pins] if self.state == 'GET BIT': self.get_bit(sym) elif self.state == 'GET EOP': self.get_eop(sym) - self.oldpins = pins elif self.state == 'WAIT IDLE': - if tuple(pins) == (0, 0): + pins = self.wait({'skip': 1}) + if pins == (0, 0): continue if self.samplenum - self.samplenum_lastedge > 1: - sym = symbols[self.options['signalling']][tuple(pins)] + sym = symbols[self.options['signalling']][pins] self.handle_idle(sym) else: - sym = symbols[self.signalling][tuple(pins)] + sym = symbols[self.signalling][pins] self.wait_for_sop(sym) - self.oldpins = pins self.edgepins = pins - elif self.state == 'INIT': - sym = symbols[self.options['signalling']][tuple(pins)] - self.handle_idle(sym) - self.oldpins = pins |