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| author | Bert Vermeulen <bert@biot.com> | 2013-10-30 15:22:10 +0100 |
|---|---|---|
| committer | Bert Vermeulen <bert@biot.com> | 2013-10-30 22:39:28 +0100 |
| commit | 69075817a626982179e5739bf0eee5e47b8a5f9e (patch) | |
| tree | 9a993e8636b2e42617c409720d89b824a3898d0f /type_logic.c | |
| parent | 56c93143f54601280a119b64b1eea8dc4b591dcb (diff) | |
| download | libsigrokdecode-69075817a626982179e5739bf0eee5e47b8a5f9e.tar.gz libsigrokdecode-69075817a626982179e5739bf0eee5e47b8a5f9e.zip | |
Documentation and coding style fixes
Diffstat (limited to 'type_logic.c')
| -rw-r--r-- | type_logic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/type_logic.c b/type_logic.c index 9f2b392..80e49f1 100644 --- a/type_logic.c +++ b/type_logic.c @@ -29,11 +29,11 @@ static PyObject *srd_logic_iter(PyObject *self) static PyObject *srd_logic_iternext(PyObject *self) { - int i; - PyObject *py_samplenum, *py_samples; srd_logic *logic; + PyObject *py_samplenum, *py_samples; uint64_t sample; uint8_t probe_samples[SRD_MAX_NUM_PROBES + 1]; + int i; logic = (srd_logic *)self; if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) { |