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author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-03-14 17:10:28 +0100 |
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committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-03-14 19:27:42 +0100 |
commit | 5e3c79fdf6fa757daaff69794fcc0bea1ab7a285 (patch) | |
tree | 0efd74219b2d98b8bf2d07ce312b2dc0274c7cfb /type_logic.c | |
parent | 1078af01aeee50c9ad9633dd477e9de575521012 (diff) | |
download | libsigrokdecode-5e3c79fdf6fa757daaff69794fcc0bea1ab7a285.tar.gz libsigrokdecode-5e3c79fdf6fa757daaff69794fcc0bea1ab7a285.zip |
uart: Minor readability nit (position of start bit in calculation)
Rephrase the bit slot index calculation for UART frames such that it
becomes more apparent whether a start bit is involved or whether an
array index needs adjustment due to Python range semantics.
This shall improve readability, and reduce the probability of off-by-one
errors during maintenance.
Diffstat (limited to 'type_logic.c')
0 files changed, 0 insertions, 0 deletions